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71.发明公开
公开(公告)号：EP1248378A1
公开(公告)日：2002-10-09
申请号：EP00900166.0
申请日：2000-01-11
申请人： Hitachi, Ltd. , TTPCOM Limited
发明人： YAMAWAKI, Taizo, Hitachi Ltd. , TANAKA, Satoshi, Hitachi Ltd. , KOKUBO, Masaru, Hitachi Ltd. , WATANABE, Kazuo, Hitachi Ltd. , KASAHARA, Masumi, Hitachi Ltd. , HORI, Kazuaki, Hitachi Ltd. , HILDERSLEY, Julian, c/o TTPCom Limited
CPC分类号： H03C3/0983 , H03C3/0925 , H03C3/0966 , H03D7/163 , H03J2200/17 , H03L7/23 , H04B1/0475 , H04B2001/0491 , H04L25/03343
摘要： There are provided a transmitter and a wireless communication terminal apparatus using the same for solving a problem of undesired spurs due to harmonics of an output signal of a frequency synthesizer, and further solving a problem of the undesired spurs occurring when the harmonics of an output signal of a crystal oscillator are mixed into a VCO to facilitate to design a circuit or a mounting substrate. The transmitter has a relationship between an output frequency of a PLL frequency conversion circuit (5) and output frequencies of frequency synthesizers (1, 2) stored therein, and the output frequencies of the frequency synthesizers (1, 2) input into the PLL frequency conversion circuit (5) are controlled on the basis of the relationship so that the undesired spurs are suppressed. Thereby, even when the undesired spurs occur in the output of the transmitter due to a crosstalk between circuits or through a substrate, which can be easily suppressed, it is therefore possible to reduce time and cost for redesigning the circuit or the substrate.
摘要翻译： 一种发射器，其中由于来自频率合成器的输出信号的谐波以及由于将来自晶体振荡器的输出信号的谐波混合到VCO中并且有助于电路和安装板的设计的不期望的寄生信号的问题，以及 公开了使用发射机的终端。 在发射机中，存储包括PLL的频率转换电路（5）的输出频率与频率合成器（1,2）的输出频率之间的关系。 通过根据关系控制输入到频率转换电路（5）的频率合成器的输出频率，抑制了不需要的寄生信号。 因此，即使由于电路和电路板之间的串扰而在发射机的输出中包含不需要的寄生信号，因此可以抑制寄生信号，从而缩短重新设计电路和电路板的时间并减少设计 成本。
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72.发明公开
公开(公告)号：EP1057252A4
公开(公告)日：2002-09-11
申请号：EP99909493
申请日：1999-02-23
申请人： TROPIAN INC
发明人： MCCUNE EARL W , SANDER WENDELL
CPC分类号： H03C3/0966 , H03B28/00 , H03C3/08 , H03C3/0941 , H03C3/095 , H03C2200/005 , H03C2200/0079
摘要： An RF modulator that allows precise, stable phase shifts to be obtained. The modulator uses a PLL structure including an auxiliary feedforward path including an adaptive gain amplifier (411) used to inject a modulation signal into the PLL at a point past a loop filter (403). A phase demodulator (419) recovers from the output of the PLL phase information which is compared in a comparator (417) to the phase information of the modulation signal. A resulting error signal is used to control the gain of the adaptive gain amplifier (411). The modulator compensates for variability of the VCO (405) and other components of the PLL.
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公开(公告)号：EP1168648A2
公开(公告)日：2002-01-02
申请号：EP01115475.4
申请日：2001-06-27
IPC分类号： H04B1/40
CPC分类号： H03C3/0966 , H03D7/165 , H03L7/16 , H03L2207/12 , H04B1/403
摘要： A phase comparator (106) compares a phase of the output signal of the quadrature modulator (104) with the phase of the signal obtained by frequency-converting the output signal of a first VCO (101) via the second VCO (102) and the first mixer (108). A PLL modulator includes a low-pass filter (107) filters a component below a predetermined frequency of the output signal of the phase comparator (106) and supplying the resulting signal to the frequency control terminal of the first VCO (101). The output signal (TS1) of the first VCO (101) is a modulated signal conforming to a modulation system having a constant envelope waveform, while the output signal of the quadrature modulator (104) is input to the first band-pass filter (110) and the output signal (TS2) of the first band-pass filter is a modulated signal conforming to a modulation system accompanied by an amplitude component as information.
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74.发明授权
公开(公告)号：EP0739090B1
公开(公告)日：2001-10-24
申请号：EP96105912.8
申请日：1996-04-16
发明人： Rapeli, Juha
IPC分类号： H03D7/16
CPC分类号： H03C3/0975 , H03B19/00 , H03B27/00 , H03C3/0941 , H03C3/0966 , H03D3/007 , H03D7/165 , H04B1/30 , H04L27/20 , H04L27/2273 , H04L2027/0028 , H04L2027/0057 , H04L2027/0067
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公开(公告)号：EP0746114B1
公开(公告)日：2001-07-18
申请号：EP96401149.8
申请日：1996-05-29
发明人： Le Corre, Jean-Luc , Robbe, Michel
CPC分类号： H03C3/0983 , H03C3/0958 , H03C3/0966 , H03L7/099 , H03L7/10 , H03L7/23 , H04B1/40
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公开(公告)号：EP1103097A1
公开(公告)日：2001-05-30
申请号：EP00939530.2
申请日：2000-06-02
IPC分类号： H03C3/09
CPC分类号： H03C3/0983 , H03C3/0966
摘要： A translation loop modulator is disclosed for a transmission circuit in a communication system. The translation loop modulator includes an input modulation unit for receiving at least one input signal that is representative of information to be modulated. The input modulation unit also receives a feedback signal, produces an intermediate modulated signal responsive to the input signal and the feedback signal. The modulator also includes a comparator unit that receives the intermediate modulated signal and a reference signal, and produces an output transmission signal responsive to the intermediate modulated signal and the reference signal. The modulator also includes feedback circuitry that is coupled to the output transmission signal, and to the reference signal. The feedback circuitry is also coupled to the input modulation unit and produces the feedback signal responsive to the output transmission signal and the reference signal.
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公开(公告)号：EP0655829B1
公开(公告)日：2001-04-18
申请号：EP94308802.1
申请日：1994-11-29
CPC分类号： H03C3/0966 , H03B29/00 , H03C3/0925 , H03C3/0941 , H03L7/0805 , H03L7/197 , H04B2215/064 , H04B2215/067
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公开(公告)号：EP1073194A2
公开(公告)日：2001-01-31
申请号：EP00119532.0
申请日：1994-11-29
IPC分类号： H03C3/09
CPC分类号： H03C3/0966 , H03B29/00 , H03C3/0925 , H03C3/0941 , H03L7/0805 , H03L7/197 , H04B2215/064 , H04B2215/067
摘要： A clock circuit includes an oscillator (15) for generating a reference frequency signal, and a spread spectrum clock generator (14) cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.
摘要翻译： 时钟电路包括用于产生参考频率信号的振荡器（15）以及与振荡器协作的扩频时钟发生器（14），用于产生扩频时钟输出信号，该扩频时钟输出信号具有基波频率和降低幅度的EMI频谱分量， 基本频率。 扩频时钟发生器最好包括一个用于产生一系列时钟脉冲的时钟脉冲发生器和一个用于对时钟脉冲发生器进行频率调制的扩频调制器，以扩大和平坦否则由时钟脉冲发生器产生的EMI频谱成分的幅度 。 扩频调制器频率调制具有相对于轮廓周期的频率偏差的特定轮廓的时钟脉冲。 还公开了包括扩频时钟电路和相关方法的电子设备。
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79.发明公开
公开(公告)号：EP0806089A1
公开(公告)日：1997-11-12
申请号：EP96900332.0
申请日：1996-01-05
发明人： RAPELI, Juha
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966 , H04B1/403 , H04L27/12
摘要： In the method and circuit for creating a modulated signal, one input signal of a phase comparator (509) of a phase-locked frequency synthesizer is an offset frequency (f2), which is created from an adjustable oscillator's (511) output signal (fTX) by mixing it with a mixer frequency (f1) and filtering the obtained result in a low pass filter (508). The other input signal is a fixed reference frequency (fr). The adjustable oscillator (511) is controlled with a control signal (VCMOD), which contains a component resulting from the phase difference of said input signals (fr, f2). Modulation is created in the output signal (fTX) of the loop by adding a frequency or phase change to at least one of the input signals (fr, f2) or their derivatives, advantageously with pulse delay technology.
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公开(公告)号：EP0801848A2
公开(公告)日：1997-10-22
申请号：EP96902002.0
申请日：1996-01-08
发明人： VAN DER VALK, Robertus, Laurentius , DUQUESNOY, Robertus, Joannes , DE RIJK, Johannes, Hermanus, Aloysius , SPIJKER, Menno, Tjeerd
CPC分类号： H03C3/0975 , H03C1/50 , H03C3/0966 , H03L7/1806
摘要： The invention relates to a circuit for frequency synthesis, comprising: a digital controlled oscillator, comprising (a) a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the digital oscillator a signal representing a control digit; and (b) a phase-locked loop which is connected to the carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter and a controlled oscillator, wherein the carry output terminal is connected to the phase detector. The digital controlled oscillator is preferably adapted to generate a signal representing a remainder, wherein a correction circuit is arranged for deriving a correction signal from the remainder. The correction circuit is connected to a combination circuit connected to one of the inputs of the phase detector or to a combination circuit incorporated in the phase-locked loop. The circuits can also be connected in cascade.
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