公开(公告)号：EP3729433B1

公开(公告)日：2024-08-21

申请号：EP18822570.0

申请日：2018-12-06

IPC分类号： G11C11/44 ,  G11C7/10 ,  G11C8/10 ,  G11C8/18 ,  G11C5/02 ,  G11C7/18 ,  G11C11/00

CPC分类号： G11C5/02 ,  G11C7/1015 ,  G11C7/18 ,  G11C8/10 ,  G11C8/18 ,  G11C11/005 ,  G11C2207/220920130101 ,  G11C11/44

公开(公告)号：EP4348647A1

公开(公告)日：2024-04-10

申请号：EP22724571.9

申请日：2022-05-02

申请人： Microsoft Technology Licensing, LLC

发明人： GE, Shaoping ,  CHAI, Chiaming ,  MARTZLOFF, Jason Philip

IPC分类号： G11C8/08 ,  G11C8/18

公开(公告)号：EP4280216A3

公开(公告)日：2024-02-07

申请号：EP23167698.2

申请日：2023-04-13

申请人： INTEL Corporation

发明人： SETHURAMAN, Saravanan ,  VERGIS, George ,  ROSE, Tonia M. ,  GOLES, John R. ,  LOVELACE, John V.

IPC分类号： G11C29/18 ,  G11C5/04 ,  G11C8/12 ,  G11C8/18 ,  G11C29/02 ,  G11C29/12 ,  G11C29/26 ,  G06F12/02 ,  G06F12/06 ,  G11C11/408 ,  G11C29/44

摘要： A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

公开(公告)号：EP3735690B1

公开(公告)日：2022-11-30

申请号：EP18800435.2

申请日：2018-10-25

发明人： SHANKAR, Harish ,  GARG, Manish ,  NADKARNI, Rahul Krishnakumar ,  KUMAR, Rajesh ,  PHAN, Michael

IPC分类号： G11C7/08 ,  G11C7/10 ,  G11C11/419 ,  G11C8/18 ,  G11C11/418

公开(公告)号：EP4057286A1

公开(公告)日：2022-09-14

申请号：EP22155735.8

申请日：2022-02-08

申请人： Samsung Electronics Co., Ltd.

发明人： JANG, Jin-Hoon ,  KIM, Kyungryun ,  KIM, Young Ju ,  LEE, Seung-Jun ,  LEE, Youngbin ,  CHOI, Yeonkyu

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C8/18

摘要： Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining an extended period of a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency during the period of the clock section, and processing a second data stream based on the data clock toggling at the reference frequency during the period of the clock section.

公开(公告)号：EP4031974A1

公开(公告)日：2022-07-27

申请号：EP20865294.1

申请日：2020-09-16

申请人： Micron Technology, Inc.

发明人： BRADSHAW, Samuel E. ,  GUNASEKARAN, Shivasankar ,  WANG, Hongyu ,  ENO, Justin M.

IPC分类号： G06F12/02 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G11C8/18

公开(公告)号：EP3853852A1

公开(公告)日：2021-07-28

申请号：EP19863864.5

申请日：2019-06-25

申请人： ATI Technologies ULC

发明人： IRSHAD, Omer ,  LEE, Joohyun

IPC分类号： G11C7/22 ,  G06F12/00 ,  G06F9/4401 ,  G11C8/18

公开(公告)号：EP3424050B1

公开(公告)日：2020-03-25

申请号：EP17710365.2

申请日：2017-02-27

申请人： Surecore Limited

发明人： COSEMANS, Stefan

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C11/418

公开(公告)号：EP3405954A1

公开(公告)日：2018-11-28

申请号：EP16825951.3

申请日：2016-12-16

申请人： Qualcomm Incorporated

发明人： GUPTA, Sharad Kumar ,  NARASIMHAN, Mukund ,  BODA, Veerabhadra Rao

IPC分类号： G11C11/418 ,  G11C8/18 ,  G11C8/10 ,  G11C8/08 ,  G11C7/22

摘要： A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

公开(公告)号：EP3266024A1

公开(公告)日：2018-01-10

申请号：EP16711404.0

申请日：2016-02-26

申请人： Northrop Grumman Systems Corporation

发明人： REOHR, William Robert ,  SHAUCK, Steven Brian ,  MILLER, Donald Lynn ,  HORNER, Jeremy William ,  JOSEPHSEN, Nathan Trent

IPC分类号： G11C11/44 ,  G11C7/22 ,  G11C7/12 ,  H01F6/00 ,  G11C8/04 ,  G11C8/18 ,  H01L39/22

CPC分类号： G11C11/44 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y25/00 ,  G11C7/12 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1693 ,  G11C19/32

摘要： One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller comprising a plurality of flux pumps configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.