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公开(公告)号：EP3490147A1
公开(公告)日：2019-05-29
申请号：EP17204038.8
申请日：2017-11-28
申请人： ams AG
发明人： Okura, Tetsuro
IPC分类号： H03K3/011 , H03K3/013 , H03K3/0231
摘要： A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (Ml, M2, M3, M4) and a plurality of controllable switches (SW11, ..., SW8, SW111, ..., SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current mirror transistors achieves a decrease of frequency degradation caused by aging effect.
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72.发明公开LATCH CIRCUITS WITH SYNCHRONOUS DATA LOADING AND SELF-TIMED ASYNCHRONOUS DATA CAPTURE 审中-公开与同步数据和充电自定时异步数据收集LOCK CIRCUITS
公开(公告)号：EP2636146A2
公开(公告)日：2013-09-11
申请号：EP11787760.5
申请日：2011-11-06
CPC分类号： H03K3/0375 , H03K3/011 , H03K3/356104
摘要： A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.
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73.发明公开
公开(公告)号：EP2520022A1
公开(公告)日：2012-11-07
申请号：EP10787976.9
申请日：2010-12-02
发明人： BHUIYAN, Ekram, H. , CHAN, Shufan
CPC分类号： H03K5/1515 , H03K3/011 , H03K17/162 , H03L1/02 , H03L7/00
摘要： A signal generating circuit (600) and method are disclosed that do not require a phase- locked- loop and a low frequency temperature- stable oscillator. The method may include generating an oscillating output signal (602) (Ik) responsive to a feedback signa (608)1, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal (654) to generate the feedback signal. The signal generating circuit (600) may include an oscillator circuit responsive to a feedback signal and a frequency- to- current conversion circuit (602responsive to a feedback signal (608) and a frequency- to- current conversion circuit (622,620) to generate a frequency dependent current signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit (612) compares the output signal with a reference signal (664) to generate the feedback signal (608) to the oscillator circuit.
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公开(公告)号：EP2176952B1
公开(公告)日：2012-06-06
申请号：EP08775296.0
申请日：2008-07-23
发明人： VANSELOW, Frank , ARNOLD, Matthias
IPC分类号： H03K3/011 , H03K3/0231 , H03L1/00 , H03L7/02 , H03L7/097
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/00 , H03L7/02
摘要： An electronic device, comprises a digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator is provided for comparing the voltage drop across the variable capacitors with a reference voltage level and for providing a DCO output clock signal. Switching means are adapted to alternately switch the variable capacitors to receive either a current from the programmable current source or to be discharged in response to an output signal of the comparator. A clock divider is coupled to an output of the comparator for dividing the DCO output clock signal by a factor N substantially greater than 1, in order to provide a divided clock signal (X). Further, a frequency monitoring stage is provided for receiving the divided clock signal and is adapted to determine the time difference of successive clock periods of the divided clock signal and to generate a feedback signal in response to the determined time difference in order to adapt the frequency of the DCO output clock signal with the feedback signal.
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公开(公告)号：EP2439846A1
公开(公告)日：2012-04-11
申请号：EP10186725.7
申请日：2010-10-06
申请人： NXP B.V.
发明人： Elend, Bernd
IPC分类号： H03K3/011 , H03K3/0231 , H03B5/04 , H03B5/20
CPC分类号： H03K3/011 , H03B5/04 , H03B5/20 , H03K3/0231 , H03L1/026
摘要： An on-chip RC oscillator comprises a resistor arrangement and a capacitor arrangement at least one of which is tuneable. Trimming settings for the resistor arrangement and/or the capacitor arrangement are stored, and a trimming setting is applied to the resistor arrangement and/or the capacitor arrangement in dependence on a sensed temperature.
摘要翻译： 片上RC振荡器包括电阻器装置和电容器装置，其中至少一个可调谐。 存储电阻器布置和/或电容器布置的修整设置，并且根据感测的温度将修整设置施加到电阻器布置和/或电容器布置。
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公开(公告)号：EP1576731B1
公开(公告)日：2012-03-21
申请号：EP03768033.7
申请日：2003-12-15
IPC分类号： H03K3/011 , H03K3/0231
CPC分类号： H03L1/022 , H03K3/011 , H03K3/0231
摘要： An R-C oscillator (200) is configured to vary the two voltage levels that are used to control the oscillation, such that the variation in oscillation frequency with temperature is minimized. A first resistor (R1) is used to control one of the voltage levels, and a second resistor (R2) having a temperature coefficient that differs from the temperature coefficient of the first transistor is used to control the other voltage level. The first resistor (R1) also controls the current used to charge and discharge the capacitor (C) used to effect the oscillation. By the appropriate choice of resistance values, the variations of the control voltages and current are such that the time to charge and discharge the capacitor (C) between the control voltages remains substantially constant with temperature. Preferably the resistance values are selected to also compensate for temperature variations in the delay of the feedback loop.
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公开(公告)号：EP2087589A4
公开(公告)日：2009-11-11
申请号：EP07839676
申请日：2007-10-17
CPC分类号： H03K3/0322 , H03K3/011 , H03K5/133 , H03K2005/00208 , H03K2005/00234
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78.发明公开INTEGRATED RELAXATION VOLTAGE CONTROLLED OSCILLATOR AND METHOD OF VOLTAGE CONTROLLED OSCILLATION 审中-公开综合RELAXATIONSSPANNUNGSGESTEUERTER振荡器和方法压控振荡器
公开(公告)号：EP1894299A1
公开(公告)日：2008-03-05
申请号：EP05760643.6
申请日：2005-06-15
发明人： CHIABURU, Liviu , DIXON, Robert
CPC分类号： H03K3/0315 , H03K3/011
摘要： Method and apparatus are provided for integrated relaxation voltage controlled oscillation. An oscillation circuit for transmitting a clock signal is provided comprising a current source (12) having a first input configured to receive a first reference potential and having a second input configured to receive a signal having a pre-determined period, and a voltage controlled oscillator (VCO) (14) coupled to the current source. The current source comprises a first capacitance (CY) and is configured to generate a reference current directly proportional to the first capacitance. The VCO has an input configured to receive the reference current. The VCO comprises a second capacitance (CX) and is configured to generate the clock signal having a period directly proportional to a ratio of the second capacitance to the first capacitance.
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公开(公告)号：EP1730840A1
公开(公告)日：2006-12-13
申请号：EP05718373.3
申请日：2005-03-11
申请人： Soisic
发明人： DESORTIAUX, Vincent
IPC分类号： H03K3/011 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/013
摘要： The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their floating body is set to a potential by means of an appropriate connection, in order to locally reduce their contribution to the overall phase noise of said circuit. It also provides a reduced phase noise master-slave circuit. This circuit includes floating body SOI type transistors, characterised in that the potential of said floating body of the transistors that (60, 61) contribute to said phase noise is set by means of an appropriate connection (64, 65).
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公开(公告)号：EP1378996B1
公开(公告)日：2006-11-29
申请号：EP03253227.7
申请日：2003-05-23
发明人： Morikawa, Yoshinao
CPC分类号： H03K3/0315 , H03K3/011 , H03K5/133 , H03K2005/00026 , H03K2005/00039 , H03K2005/0013 , H03K2005/00143 , H03K2005/00208
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