公开(公告)号：EP1376413A1

公开(公告)日：2004-01-02

申请号：EP02425415.3

申请日：2002-06-25

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics Ltd.

发明人： Blasi, Gianluca ,  Tayal, Reenee

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  Y10S707/99933

摘要： A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language comprises a repository (10) storing a general set of self-checking tests applicable to the integrated circuits, means for entering behaviour data (21) of an integrated circuit model (20), means for entering configuration data (22) of the integrated circuit model and means for automatically generating test benches (30) in said Hardware Description Language, which means are configured to make a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behaviour data.

摘要翻译： 一种用于验证由硬件描述语言中的模型指定的集成电路的基于计算机的测试台发生器（1）包括存储适用于集成电路的一般的一组自检测试的存储库（10），用于输入行为数据（21）的装置 集成电路模型（20）的装置，用于输入集成电路模型的配置数据（22）的装置和用于在所述硬件描述语言中自动生成测试台（30）的装置，所述装置被配置为进行适当的选择和设置 根据指定的集成电路模型，配置和行为数据从存储库进行测试。

公开(公告)号：EP1320990A1

公开(公告)日：2003-06-25

申请号：EP01967527.1

申请日：2001-09-19

申请人： STMicroelectronics, Ltd.

发明人： HAYDOCK, Steven

IPC分类号： H04N5/00

CPC分类号： H04N21/434

摘要： Data reception apparatus for receiving and processing a data stream including a stream of data units, the data apparatus comprising: a buffer; a data reception controller for receiving data units from the data stream, storing received data units in the buffer, and if the amount of data from the data stream that is stored in the buffer exceeds a predetermined amount, generating a buffer load interrupt for the data stream; and a processor responsive to the buffer load interrupt to: a) disable handling of further buffer load interrupts for the data stream; and b) repeatedly activate a routine to process a single data unit from the data stream that is stored in the buffer until all the data units in the buffer have been processed and then reset the buffer.

公开(公告)号：EP1271782A2

公开(公告)日：2003-01-02

申请号：EP02012610.8

申请日：2002-06-06

申请人： STMicroelectronics Ltd.

发明人： Singh, Moninder ,  Chaudhry, Anurag

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A field programmable logic device comprising at least two independently configurable embedded memory structures wherein said memory structures differ in at least one of the following parameter

memory size
available configuration depths
available configuration widths
for efficient memory utilization.

摘要翻译： 现场可编程逻辑器件，包括worin所述存储器结构分化成以下参数存储器大小可用配置深度可用的配置宽度用于高效存储器利用率中的至少一个的至少两个unabhängig配置嵌入式存储器结构。

公开(公告)号：EP1262866A1

公开(公告)日：2002-12-04

申请号：EP01304837.6

申请日：2001-06-01

申请人： STMicroelectronics, Ltd.

发明人： Cordero, Rodrigo

IPC分类号： G06F7/02 ,  H04N7/26

CPC分类号： G06F7/026 ,  H04N19/89 ,  H04N21/434 ,  H04N21/44209

摘要： A method which determines the validity of information contained in a data stream, said information falling within a predetermined range when valid, said method comprises the steps of selecting a first part of said of said information, said first part being more significant than a remainder of said information; comparing said first part with one or more corresponding parts of one or more values defining said predetermined range. Determining from said comparing step if said information is or could be within said predetermined range.

摘要翻译： 一种确定数据流中包含的信息的有效性的方法，所述信息在有效时落在预定范围内，所述方法包括以下步骤：选择所述信息的所述第一部分，所述第一部分比其余部分更有意义 信息说 将所述第一部分与限定所述预定范围的一个或多个值的一个或多个对应部分进行比较。 如果所述信息是或可以在所述预定范围内，则从所述比较步骤确定。

公开(公告)号：EP1197969A1

公开(公告)日：2002-04-17

申请号：EP01307194.9

申请日：2001-08-23

申请人： STMicroelectronics, Ltd.

发明人： Hammond, Paul ,  Barnes, William

IPC分类号： G11C29/00

CPC分类号： G11C29/32

摘要： The present invention proposes a method of disabling a particular decoder output during scan-mode testing without impacting the critical path during either scan-mode or the normal mode of operation. During scan-mode testing a known bit stream may be programmed into latches and provides a means of functional testing the device in question. Three embodiments are used in conjunction with a disable driver to pull an intermediate node HIGH. The intermediate node is inverted by an output driver, which disables the relevant decoder output. The first embodiment involves using a full CMOS gate, the second embodiment uses ratio logic and the third uses a weak pull-up resistor.

摘要翻译： 本发明提出了一种在扫描模式测试期间禁用特定解码器输出的方法，而不影响在扫描模式或正常操作模式期间的关键路径。 在扫描模式测试期间，已知比特流可以被编程到锁存器中，并提供对所讨论的设备进行功能测试的手段。 三个实施例与禁用驱动器结合使用以将中间节点拉高。 中间节点由输出驱动器反相，禁用相关的解码器输出。 第一实施例涉及使用全CMOS栅极，第二实施例使用比率逻辑，第三实施例使用弱上拉电阻。

公开(公告)号：EP1148421A1

公开(公告)日：2001-10-24

申请号：EP01300903.0

申请日：2001-02-01

申请人： STMicroelectronics, Ltd.

发明人： Philips, Mark

IPC分类号： G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3656

摘要： To enable a processor connected to a host computer to run programs that are dynamically loaded by the host, a stack is loaded into its memory. The location of the stack, or information enabling that location to be found is stored in a memory location reserved as a vector. The programs are then dynamically loaded into said memory; and a set location in the stack is used to store the entry point into the dynamically loaded file.

摘要翻译： 为了使连接到主机的处理器能够运行由主机动态加载的程序，堆栈将被加载到其内存中。 堆栈的位置或能够找到该位置的信息被存储在保留作为向量的存储器位置中。 然后将程序动态地加载到所述存储器中; 并且堆栈中的设置位置用于将入口点存储到动态加载的文件中。

公开(公告)号：EP1098438A1

公开(公告)日：2001-05-09

申请号：EP00309651.8

申请日：2000-11-01

申请人： STMicroelectronics, Ltd.

发明人： Barnes, William Bryan

IPC分类号： H03K3/356 ,  H03K3/012

CPC分类号： H03K3/356113 ,  H03K3/012

摘要： A complementary logic circuit is provided which provides improved switching times over known complementary logic circuits. The circuit includes a further n-type transistor connected in series between a p-type and an n-type transistor. This additional n-type transistor has its gate permanently connected to an upper supply voltage, Vdd. When switching occurs the n-type transistor is effectively open circuit. This allows the first n-type transistor to switch on by a substantial amount quite quickly without 'fighting' the presently conducting p-type transistor. When the first n-type transistor has been turned substantially on does the second transistor becomes conductive. Then the p-type transistor is substantially turned off and no longer opposes the turning on of the first n-type transistor.

摘要翻译： 提供了一种互补逻辑电路，其提供了比已知的互补逻辑电路更好的切换时间。 该电路包括在p型和n型晶体管之间串联连接的另一n型晶体管。 该附加的n型晶体管的栅极永久地连接到上电源电压Vdd。 当切换发生时，n型晶体管有效开路。 这允许第一n型晶体管相当快地接通大量，而不会使当前导电的p型晶体管“战斗”。 当第一n型晶体管已基本上导通时，第二晶体管导通。 然后，p型晶体管基本截止，并且不再与第一n型晶体管的导通相对。

公开(公告)号：EP0993225A1

公开(公告)日：2000-04-12

申请号：EP99307885.6

申请日：1999-10-06

申请人： Stmicroelectronics, Ltd.

发明人： Richards, Neil ,  Panesar, Gajinder Singh ,  Carey, John ,  Thompson, Peter

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5653 ,  H04L2012/5681

摘要： A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.

摘要翻译： 一种数据接收单元，用于通过数据信道接收多个数据流，数据流被接收为数据量，并且每个数据量包括包括来自数据流的数据和识别该数据流的标识部分的数据部分， 数据接收单元，包括：数据流存储器，包括多个数据流存储区域，每个数据流存储区域用于存储来自一组数据流中的相应一个的数据;以及逃生缓冲器; 第一存储信息存储器，用于保存用于便于从所述数据流集合中的数据的相应数据流存储区域中存储的第一存储信息; 以及数据存储控制器，用于针对每个接收的数据量，接收所述数据量的身份部分并执行存储操作，包括：访问所述第一存储信息存储器; 并且如果所述第一存储信息存储器保存由所述身份部分标识的数据流的第一存储信息，则将所述数据量的数据部分存储在与所述数据流对应的数据流存储区域中; 并且如果所述第一存储信息存储器不存储由所述身份部分标识的数据流的第一存储信息，则将所述数据量的数据部分存储在所述转义缓冲器中; 以及连接到逃逸缓冲器以用于执行组装操作的处理单元，包括执行将存储在转义缓冲器中的信息组合成相应数据流的步骤。

公开(公告)号：EP0993220A1

公开(公告)日：2000-04-12

申请号：EP99307879.9

申请日：1999-10-06

申请人： Stmicroelectronics, Ltd.

发明人： Richards, Neil ,  Panesar, Gajinder Singh ,  Carey, John ,  Thompson, Peter

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5653 ,  H04L2012/5681

摘要： A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.

摘要翻译： 一种数据接收单元，用于通过数据信道接收多个数据流，所述数据流被接收为数据量，并且每个数据量包括包括来自数据流的数据和识别该数据流的标识部分的数据部分， 数据接收单元，包括：数据流存储器，包括多个数据流存储区域，每个数据流存储区域用于存储来自一组数据流中的相应一个的数据;以及逃生缓冲器; 第一存储信息存储器，用于保存用于便于从所述数据流集合中的数据的相应数据流存储区域中存储的第一存储信息; 以及数据存储控制器，用于针对每个接收的数据量，接收所述数据量的身份部分并执行存储操作，包括：访问所述第一存储信息存储器; 并且如果所述第一存储信息存储器保存由所述身份部分标识的数据流的第一存储信息，则将所述数据量的数据部分存储在与所述数据流对应的数据流存储区域中; 并且如果所述第一存储信息存储器不存储由所述身份部分标识的数据流的第一存储信息，则将所述数据量的数据部分存储在所述转义缓冲器中; 以及连接到逃逸缓冲器以用于执行组装操作的处理单元，包括执行将存储在转义缓冲器中的信息组合成相应数据流的步骤。

公开(公告)号：EP0905610A1

公开(公告)日：1999-03-31

申请号：EP98307887.4

申请日：1998-09-29

申请人： Stmicroelectronics, Ltd.

发明人： Warren, Robert

IPC分类号： G06F5/06

CPC分类号： G06F5/10

摘要： Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchroniser for synchronising the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronised control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

摘要翻译： 描述了用于将信息从第一定时环境传送到第二定时环境的电路。 该电路包括双端口RAM，该双端口RAM具有响应于第一定时信号的第一端口和响应于第二定时信号的第二端口，响应于第一定时信号的第一控制电路，用于控制数据的存储 在双端口RAM中通过第一端口并且用于产生指示数据存储在双端口RAM中的控制信号。 该电路还包括用于使控制信号与第二定时信号同步的同步器和响应于第二定时信号和同步的控制信号并且用于控制通过第二定时信号的第二端口检索存储的数据的第二控制电路 双端口RAM。