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公开(公告)号:EP4020231B1
公开(公告)日:2024-05-01
申请号:EP21198841.5
申请日:2021-09-24
IPC分类号: G06F12/0886 , G06F9/30 , G06F9/38
CPC分类号: G06F12/0886 , G06F2212/40120130101 , G06F2212/102420130101 , G06F9/3004 , G06F9/3836 , G06F9/30145
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公开(公告)号:EP3913495B1
公开(公告)日:2024-05-01
申请号:EP21305636.9
申请日:2021-05-14
IPC分类号: G06F16/23
CPC分类号: G06F16/2308
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公开(公告)号:EP4357080A1
公开(公告)日:2024-04-24
申请号:EP23204426.3
申请日:2023-10-18
申请人: Max Co., Ltd.
发明人: MOCHIZUKI, Kazuya
IPC分类号: B25C1/00
CPC分类号: B25C1/003
摘要: A handheld tool includes a magazine accommodating a plurality of fasteners coupled by a coupling band, a lid portion opening and closing the magazine, a nose portion having an injection passage and an injection port, a supply passage connecting the injection passage and the magazine for feeding the fasteners coupled by the coupling band to the injection passage; and a driver bit separating the fasteners of the injection passage from the coupling band and driving the fasteners toward the injection port. The nose portion has a discharge port for discharging the coupling band from which the fasteners are separated. The injection passage and the discharge port have an opening portion on a lateral side perpendicular to the extending direction of the injection passage, and the lid portion exposes and covers the opening portion.
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公开(公告)号:EP3924838B1
公开(公告)日:2024-04-24
申请号:EP20703488.5
申请日:2020-02-13
IPC分类号: G06F16/2455
CPC分类号: G06F16/24552
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公开(公告)号:EP4354303A2
公开(公告)日:2024-04-17
申请号:EP24153964.2
申请日:2017-07-01
申请人: Intel Corporation
发明人: Valentine, Robert , Baum, Dan , Sperber, Zeev , Corbal, Jesus , Ould-Ahmed-Vall, ElMoustapha , Toll, Bret L. , Charney, Mark J. , Ziv, Barukh , Heinecke, Alexander , Girkar, Milind , Rubanovich, Simon
IPC分类号: G06F12/02
CPC分类号: G06F9/30036 , G06F2212/45520130101 , G06F12/0207 , G06F2212/45420130101 , G06F9/3001 , G06F7/5443 , G06F9/3861 , G06F9/30014 , G06F9/3016
摘要: Embodiments detailed herein relate to matrix operations. For example, in some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, for identifying a first plurality of source vectors, for identifying a second plurality of source vectors, and for identifying a plurality of destination vectors; and execution circuitry to execute the decoded instruction to, for each data element position of each of the identified first plurality of source vectors: subtract, from a first data value at that data element position, a second data value at a corresponding data element position of a corresponding one of the identified second plurality of source vectors, and store a result of the subtraction into a corresponding data element position of a corresponding one of the identified plurality of destination vectors.
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公开(公告)号:EP4351465A1
公开(公告)日:2024-04-17
申请号:EP22737993.0
申请日:2022-06-07
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87.
公开(公告)号:EP4328744A3
公开(公告)日:2024-04-17
申请号:EP24152035.2
申请日:2019-06-25
申请人: INTEL Corporation
CPC分类号: G06F7/4876 , G06F7/5324 , G06F9/30014 , G06F9/30025
摘要: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes a plurality of cores to execute instructions. Each core of the plurality of cores comprises: a Level-1 (L1) instruction cache to store the instructions and an L1 data cache to store corresponding data; a plurality of vector registers to store a plurality of packed data elements, including single-precision floating-point data elements and reduced precision floating-point data elements having fewer mantissa bits than the single-precision floating point data elements and a same number of exponent bits as the single-precision floating point format data elements; and execution circuitry to execute an instruction to generate a dot product with a first pair of the reduced precision floating-point data elements and a corresponding second pair of the reduced precision floating-point data elements. The execution circuitry is to: generate a plurality of single precision floating-point products corresponding to the first pair and the second pair of the reduced precision floating-point data elements; and accumulate the plurality of single precision floating-point products to generate a single precision floating-point result data element.
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公开(公告)号:EP4328536A3
公开(公告)日:2024-04-17
申请号:EP24151898.4
申请日:2022-02-25
申请人: Heckler & Koch GmbH
发明人: STAIGER, Markus , SCHEUERMANN, Mark , KOPF, Johannes Alexander , GEBERT, Dietrich , RIMPF, Dieter
IPC分类号: F41A19/01
CPC分类号: F41A19/01
摘要: Die Erfindung betrifft eine Schusswaffenanalysevorrichtung zur Bestimmung von für eine Schusswaffe (7) indikativen Parametern aus einer Schussabgabe sowie ein entsprechendes Verfahren, eine entsprechende Schusswaffe und ein Computerprogrammprodukt. Die Vorrichtung umfasst eine Spannungserzeugungseinheit (401), die während eines bei einer Schussabgabe erfolgenden Vor- und/oder Rücklaufs eines beweglichen Waffenteils (120) eine Wechselspannung (Ue) erzeugt. Die Vorrichtung ist gekennzeichnet durch eine Signalverarbeitungseinheit (410), die aus der erzeugten Wechselspannung (Ue) ein Messsignal (IN+) erzeugt, eine Signalauswerteeinheit (420), die einen ersten und einen zweiten Zeitpunkt (t701-t705, t702-t706) während des Vor- und/oder Rücklaufs des beweglichen Waffenteils (120) bestimmt und eine Zeitbestimmungseinheit (450), die eine Zeitabschnittsdauer zwischen dem ersten und dem zweiten Zeitpunkt (t701-t705, t702-t706) bestimmt.
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公开(公告)号:EP4350746A1
公开(公告)日:2024-04-10
申请号:EP21943040.2
申请日:2021-05-27
IPC分类号: H01L21/338 , H01L29/812
摘要: A field-effect transistor (100a) includes a channel layer (102) made of a compound semiconductor and formed on a substrate (101); a gate electrode (103) formed on the channel layer (102); and a source electrode (104) and a drain electrode (105), which are formed with the gate electrode (103) interposed therebetween. At least one of the source electrode (104) and the drain electrode (105) is formed on a substrate (101) side of the channel layer (102).
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公开(公告)号:EP4089019B1
公开(公告)日:2024-04-10
申请号:EP22172308.3
申请日:2016-07-21
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