公开(公告)号：EP3140999A1

公开(公告)日：2017-03-15

申请号：EP14730435.6

申请日：2014-05-07

申请人： Epcos AG

发明人： CONSO, Fabrizio

IPC分类号： H04R29/00

CPC分类号： H04R3/06 ,  H03K5/26 ,  H04R1/04 ,  H04R19/04 ,  H04R29/004 ,  H04R2201/003

摘要： A MEMS microphone which is able to be set to different modes of operation is proposed that requires one single pin to apply an external clock frequency to the microphone. The applied clock frequency is selected according to a desired mode of operation and the microphone detects the applied frequency and sets the mode of operation.

摘要翻译： 提出了一种能够设置为不同操作模式的MEMS麦克风，其需要一个单个引脚来向麦克风施加外部时钟频率。 应用的时钟频率根据所需的操作模式选择，麦克风检测所施加的频率并设置操作模式。

公开(公告)号：EP3107218A1

公开(公告)日：2016-12-21

申请号：EP15172905.0

申请日：2015-06-19

申请人： GWF MessSysteme AG

发明人： Mathis, Peter

IPC分类号： H04B3/54 ,  H03K5/00

CPC分类号： H04B3/548 ,  H03K5/26 ,  H03K21/02 ,  H03K2005/00045 ,  H04B2203/54

摘要： Das Verfahren dient der Übertragung von Signalen und Daten innerhalb wenigstens einer ersten und einer zweiten Übertragungsphase (TP1, TP2), die synchron oder asynchron aufeinander folgen, zwischen einer ersten Kommunikationseinheit (L) und wenigstens einer zweiten Kommunikationseinheit (Z), die eine zentrale Prozessoreinheit (CPU), eine Speichereinheit (M), in der ein Betriebsprogramm (OP) abgelegt ist, und wenigstens einen ersten Ereignisgenerator (EG1) umfasst, der über eine Übertragungsleitung (W) zwischen den beiden Kommunikationseinheiten (L, Z) übertragene Signalfolgen (SL, SZ) unabhängig von der zentralen Prozessoreinheit (CPU) überwacht und für Ereignisse während der Datenübertragung, die gemäss dem angewendeten Übertragungsprotokoll auftreten, Ereignismeldungen (e1, e2) generiert, die zur zentralen Prozessoreinheit (CPU) und/oder zu wenigstens einem Ereignisanwender (EU1) übertragen werden.

摘要翻译： 该方法用于在第一通信单元（L）和至少一个第二通信单元（Z）之间的同步或异步地彼此跟随的至少一个第一和第二传输阶段（TP1，TP2）中传输信号和数据 ），其包括中央处理单元（CPU），存储有操作程序（OP）的存储单元（M）以及独立于中央处理单元（CPU）的至少一个事件发生器（EG1），其监视 通过两个通信单元（L，Z）之间的传输线（W）发送的信号序列（SL，SZ），并根据所应用的传输协议生成在数据传输期间出现的事件的事件消息（e1，e2）， 被发送到中央处理单元（CPU）和/或至少一个事件用户（EU1）。

公开(公告)号：EP3062438A1

公开(公告)日：2016-08-31

申请号：EP16000425.5

申请日：2016-02-22

申请人： Linear Technology Corporation

发明人： MYERS, John Perry

IPC分类号： H03D3/00 ,  H03D7/14 ,  H03B27/00 ,  H04L27/00

CPC分类号： H03H11/18 ,  H03B27/00 ,  H03D3/009 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0021 ,  H03D2200/0043 ,  H03H11/22 ,  H03K5/02 ,  H03K5/26 ,  H03K2005/00286

摘要： A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.

摘要翻译： 补偿相位误差的方法和系统。 相位误差补偿电路被配置为产生相位校正的正交Q输出信号和对应的相位校正的同相I输出信号，该电路包括第一跨导电路，其被配置为将与I输入电压信号相关的电压信号 到I当前信号。 第二跨导电路被配置为将与Q输入信号相关的电压信号转换为Q电流信号。 第一乘法器电路被配置为将Q电流信号乘以Q缩放常数。 第二乘法器电路被配置为将I电流信号乘以I定标常数。 I夏天用缩放的Q信号加上I电流信号。 Q夏令会与缩放的I信号相加Q电流信号。

公开(公告)号：EP2993811A2

公开(公告)日：2016-03-09

申请号：EP15178788.4

申请日：2015-07-29

申请人： FUJITSU LIMITED

发明人： SHIMURA, Toshihiro

IPC分类号： H04B17/12 ,  H04B7/04 ,  H01Q3/26

CPC分类号： H03K5/26 ,  G01R25/005 ,  G01R25/04 ,  H01Q3/267 ,  H01Q3/2694 ,  H01Q3/38 ,  H04B7/04 ,  H04B17/104 ,  H04B17/12

摘要： A phase adjustment device includes: a detection signal generator configured to generate a pair of first and second detection signals for detecting a phase difference between two signals whose phases have been adjusted by two phase adjusters, respectively, a maximum sensitivity phase difference of one of the first and second detection signals being not overlap with that of the other, and detection sensitivity of the phase difference becoming maximum at the maximum sensitivity phase difference; a detection signal selector configured to select one of the first and second detection signals whose predetermined range around the maximum sensitivity phase difference covers a preset phase difference; and a phase controller configured to control an amount of phase-adjusting by at least one of the two phase adjusters based on a difference between the phase difference detected within the predetermined range using the selected detection signal and the preset phase difference.

公开(公告)号：EP2959588A1

公开(公告)日：2015-12-30

申请号：EP14711043.1

申请日：2014-02-24

申请人： Microchip Technology Incorporated

发明人： BUCH, Fredrik ,  ALBINA, Cristian ,  YUENYONGSGOOL, Yong

IPC分类号： H03L7/095 ,  H03L7/087 ,  H03L7/089

CPC分类号： H03L7/087 ,  H03K5/26 ,  H03L7/089 ,  H03L7/095 ,  H03L7/097

摘要： A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.

公开(公告)号：EP2897319A1

公开(公告)日：2015-07-22

申请号：EP14004398.5

申请日：2014-12-23

申请人： Broadcom Corporation

发明人： Valliappan, Magesh ,  Momtaz, Afshin ,  Kocaman, Namik ,  Parthasarathy, Vasudevan

IPC分类号： H04L7/033

CPC分类号： H03K5/26 ,  H04B7/155 ,  H04L7/033

摘要： A frequency estimation circuit for a reference-less repeater circuit comprises an edge detector configured to measure time periods between edge-to-edge transitions in a data stream within a predetermined time interval, resulting in a plurality of edge-to-edge time periods; and a processor configured to categorize the plurality of edge-to-edge time periods into a plurality of representative groups, each representative group having a representative time period that is an integer multiple of a sampling unit time period; to determine a number of virtual transitions in the predetermined time interval based on the categorized plurality of edge-to-edge time periods and to determine a frequency estimate of the data stream based on the number of virtual transitions in the predetermined time interval.

公开(公告)号：EP2798742A4

公开(公告)日：2015-07-08

申请号：EP11878713

申请日：2011-12-30

申请人： INTEL CORP

发明人： ROYTMAN EDUARD EDI ,  NAGARAJAN MAHALINGAM MALI ,  VEMPADA PRADEEP R

IPC分类号： H03K19/0175 ,  H03F3/45 ,  H04L25/02

CPC分类号： H03K5/1565 ,  H03F3/45071 ,  H03F2200/144 ,  H03F2200/165 ,  H03F2200/375 ,  H03F2200/78 ,  H03K5/26 ,  H04L25/0274 ,  H04L25/0296 ,  H04L25/03878

摘要： In some embodiments, a differential amplifier with duty cycle correction is provided.

公开(公告)号：EP2717469A2

公开(公告)日：2014-04-09

申请号：EP13181992.2

申请日：2013-08-28

申请人： LSIS Co., Ltd.

发明人： Park, Kang Hee

IPC分类号： H03K5/19 ,  H03K5/26 ,  G01R23/00 ,  G01R23/10

CPC分类号： H03K21/40 ,  G01R23/10 ,  G01R23/15 ,  H03K5/19 ,  H03K5/26 ,  H03K21/38

摘要： An apparatus (30) and method for detecting a cut-off frequency of a pulse signal (First Pulse Signal) is provided to detect a cut-off frequency of a pulse signal, in a case a frequency of an inputted pulse signal exceeds a maximum rated speed due to various reasons including noises generated by a system environment or an encoder, or system design error, whereby an appropriate action thereto can be taken, the apparatus (30) including an input processor (31) configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter (32) configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor (33) configured to reset the counter at every predetermined (set) period, and a detector (34) configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.

摘要翻译： 在输入的脉冲信号的频率超过最大值的情况下，提供用于检测脉冲信号（第一脉冲信号）的截止频率的装置（30）和方法以检测脉冲信号的截止频率 由于各种原因引起的额定速度，包括由系统环境或编码器产生的噪声或系统设计错误，由此可以采取适当的动作，所述装置（30）包括输入处理器（31），其被配置为产生第二脉冲信号 在第一脉冲信号的上升沿和下降沿出现的情况下，在作为监视对象的脉冲信号的第一脉冲信号被输入的情况下，配置为对时钟信号进行计数的计数器（32） 相对于由输入处理器产生的第二脉冲信号，复位处理器（33）被配置为以每个预定（设置）周期复位计数器;以及检测器（34），被配置为产生和输出检测的截止频率 信号，在一种情况下 计数器的输出值在规定期间内超过规定（设定）阈值。

公开(公告)号：EP2267574A3

公开(公告)日：2011-11-23

申请号：EP10166486.0

申请日：2010-06-18

申请人： STMicroelectronics (Research & Development) Limited

发明人： Trimmer, Mark

IPC分类号： G06F1/14 ,  H03K5/22 ,  G01R31/317

CPC分类号： H03K5/19 ,  G06F1/14 ,  H03K5/26

摘要： There is provided a circuit and method for detecting a bad clock condition on a clock signal, the method comprising: sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal, such that a respective first plurality of samples are produced; determining whether all of the first plurality of samples have a first logic state; sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal, such that a respective second plurality of samples are produced; determining whether all of the second plurality of samples have a second logic state; and determining that the bad clock condition exists on the clock signal if at least one of the following conditions is met: it is determined that all of the first plurality of samples have the first logic state, or it is determined that all of the second plurality of samples have the second logic state.

公开(公告)号：EP2113142A2

公开(公告)日：2009-11-04

申请号：EP08709947.9

申请日：2008-01-31

申请人： NXP B.V.

发明人： HUARD, Vincent

IPC分类号： H03K5/135 ,  G06F1/04 ,  H04L7/033

CPC分类号： H03K5/135 ,  G06F1/04 ,  H03K5/26 ,  H03K2005/00084 ,  H03L7/00

摘要： A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.