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148 条记录 (耗时 0.042 秒)

    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO
    85.
    发明公开
    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO 审中-实审

    公开(公告)号：EP4358416A3

    公开(公告)日：2024-05-08

    申请号：EP24160345.5

    申请日：2018-11-07

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： LIU, Qingchao ,  CHEN, Xixian ,  NEZAMI, Yashar

    IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/13 ,  H03M13/27

    CPC分类号： H03M13/116 ,  H03M13/2707 ,  H03M13/635 ,  H03M13/6561 ,  H03M13/6569 ,  H03M13/13

    摘要： Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

    REMOVAL OF DUMMY BITS PRIOR TO BIT COLLECTION FOR 3GPP LTE CIRCULAR BUFFER RATE MATCHING
    86.
    发明公开
    REMOVAL OF DUMMY BITS PRIOR TO BIT COLLECTION FOR 3GPP LTE CIRCULAR BUFFER RATE MATCHING 审中-公开

    公开(公告)号：EP3367575A1

    公开(公告)日：2018-08-29

    申请号：EP18156817.1

    申请日：2018-02-14

    申请人： Ceva D.S.P. Ltd.

    发明人： David, Levy

    IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L1/00

    CPC分类号： H04W28/22 ,  H03M13/271 ,  H03M13/2957 ,  H03M13/635 ,  H03M13/6525 ,  H04L1/0013 ,  H04L69/22

    摘要： A method and a logic circuit for rate matching for three equally sized bit streams, including: prepending each of the bit streams with null bits (220); permuting the first two bit streams according to a first permutation pattern (230); permuting the third bit stream based on the first permutation pattern (240); transposing the three bit streams (250); shuffling the second and third bit streams (260); removing the null bits from the first bit stream (270) and from the shuffled bit stream (280), wherein location of the null bits in the first bit stream is based only on a number of prepended null bits and the first permutation pattern and location of the null bits in the shuffled bit stream is based only on the number of prepended null bits, the first permutation pattern, and a null index related to the number of prepended null bits; and generating a combined bit stream from the three bit streams (290). The disclosed rate matching differs from the circular buffer rate matching as specified by 3GPP TS 36.212 in that the pruning or removal dummy bits is performed prior to the bit collection.

    VARIABLE CODE RATE SOLID-STATE DRIVE
    87.
    发明公开
    VARIABLE CODE RATE SOLID-STATE DRIVE 审中-公开
    可变代码速率固态驱动器

    公开(公告)号：EP3314769A1

    公开(公告)日：2018-05-02

    申请号：EP16710057.7

    申请日：2016-03-03

    申请人： Xilinx, Inc.

    发明人： DICK, Christopher, H.

    IPC分类号： H03M13/11 ,  H03M13/35 ,  G06F11/10

    CPC分类号： G06F11/1068 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/353 ,  H03M13/635 ,  H03M13/6393

    摘要： An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.

    METHOD AND APPARATUS FOR RATE MATCHING OF POLAR CODE
    89.
    发明公开
    METHOD AND APPARATUS FOR RATE MATCHING OF POLAR CODE 审中-公开
    VERFAHREN UND VORRICHTUNGFÜRRATENANPASSUNG EINES POLAREN CODES

    公开(公告)号：EP3079290A1

    公开(公告)日：2016-10-12

    申请号：EP14883336.1

    申请日：2014-02-21

    申请人： Huawei Technologies Co., Ltd.

    发明人： SHEN, Hui ,  LI, Bin ,  SHI, Yuchen

    IPC分类号： H04L1/00

    CPC分类号： H04L1/0057 ,  H03M13/13 ,  H03M13/2792 ,  H03M13/635 ,  H04L1/0041 ,  H04L1/0067 ,  H04L1/0069 ,  H04L1/0071 ,  H04L1/1812

    摘要： A rate matching method for a polar code is provided, where the method includes: acquiring a congruential sequence according to a code length of a target polar code; performing sorting processing on the congruential sequence according to a preset rule, to acquire a reference sequence; determining a mapping function according to the congruential sequence and the reference sequence; and interleaving the target polar code according to the mapping function, to generate interleaved output bits. The congruential sequence is determined based on the code length of the polar code, and interleaving of the target polar code is implemented by using the congruential sequence, which can enable a sequence of bits obtained after the interleaving to have a more uniform structure, can reduce a frame error rate and improve HARQ performance, thereby improving reliability of communication; can be applicable to rate matching processes of polar codes of various code lengths, and has good commonality and practicality.

    摘要翻译： 提供一种用于极性码的速率匹配方法，其中该方法包括：根据目标极性码的码长获取同余序列; 根据预设规则对同余序列执行排序处理，以获取参考序列; 根据同余序列和参考序列确定映射函数; 并根据映射函数对目标极性码进行交织，以产生交织的输出比特。 同步序列是根据极性码的码长确定的，目标极性码的交织是通过使用同余序列来实现的，这可以使交织后得到的比特序列具有更均匀的结构，可以减少 帧错误率并提高HARQ性能，从而提高通信的可靠性; 可适用于各种码长极性码的速率匹配过程，具有良好的通用性和实用性。

    CIRCUIT AND METHOD FOR PARALLEL PERFORATION IN SPEED RATE MATCHING
    90.
    发明公开
    CIRCUIT AND METHOD FOR PARALLEL PERFORATION IN SPEED RATE MATCHING 有权
    电路及方法并行穿孔的速度速率调整

    公开(公告)号：EP2451108A4

    公开(公告)日：2016-08-17

    申请号：EP10793603

    申请日：2010-06-29

    申请人： ZTE CORP

    发明人： WEN ZIYU

    IPC分类号： H04L1/00 ,  H03M13/00

    CPC分类号： H04L1/0067 ,  H03M13/635 ,  H03M13/6362 ,  H03M13/6525 ,  H03M13/6561 ,  H04L1/0043

    摘要： The present invention discloses a circuit and a method for parallel perforation in rate matching, which can reduce the perforation processing time delay to satisfy the requirements of a Long Term Evolution (LTE). Both the circuit and the method can adopt three selector arrays and three register groups. Specifically, the first selector array is configured to remove null bits in input data and output the remaining data to the first register group; the second selector array is configured to combine the first register group and the third register group and then output the combined data to the second register group; during the combination, the valid data in the third register group are preferentially selected, and then the data in the first register group are selected; when the second register group is full, the data therein are output to the exterior as the results of the perforation processing. Further, the third selector array is configured to output remaining valid data in the first selector group to the third register group if the valid data in the first selector group are not used out while combining the first register group and the third register group by the second selector array.