摘要:
The invention relates to a method for authenticating a plurality of slave devices (D1-D3) connected to a master device (CPU), including the steps consisting in: the master device generating and sending a respective challenge (c1-c3) to each slave device; a response (r1-r3) to the respective challenge being generated in each slave device and sent to the master device; the master device verifying the response (r3) of one of the slave devices (D3); the master device returning the remaining responses to respective slave devices other than those that generated the responses; and each slave device (D2, D3) verifying the response that was returned to it by the master device and transmitting the result of the verification to the master device.
摘要:
L'invention concerne un dispositif (ND1) d'émission de données par couplage inductif, comprenant un circuit d'antenne inductif accordé (ACT) et un circuit de modulation d'amplitude (MCT1) pour appliquer au circuit d'antenne des salves (B3) d'un signal périodique (Slm), l'amplitude de chaque salve étant délimitée par un signal d'enveloppe présentant un front montant et un front descendant. Selon l'invention, le circuit de modulation est configuré pour conformer au moins le front descendant du signal d'enveloppe de manière que la dérivée première du front descendant soit continue, pour atténuer ou supprimer des oscillations transitoires du signal d'antenne pouvant être générées par l'application au circuit d'antenne des salves du signal périodique.
摘要:
The invention relates to a communication interface, comprising an input terminal (Rx) designed to receive a logic signal from a remote interface (IF2); a logic level discriminator (12) coupled to the input terminal; a peak detector (14) connected so as to store the peak value of the signal on the input terminal; and a voltage follower (16) connected so as to provide to the discriminator an auxiliary supply voltage (Vdd2') based on the value provided by the peak detector. The interface includes a device for protection against electrostatic discharges, comprising a first diode (D1) and an RC circuit forming the peak detector, which are connected in series between the input terminal (Rx) and a first supply line (Vss1); a transistor (MN1) connected between the first supply line (Vss1) and the input terminal (Rx) by the first diode (D1); and an inverter (42) configured to switch the transistor on when the voltage across the terminals of the capacitor of the RC circuit is below a threshold.
摘要:
The invention relates to a method for adjusting an oscillator clock frequency, comprising steps consisting in: applying a first control value (S1) to a first oscillator (OSC1); applying a second control value (S2) different from the first control value to a second oscillator (OSC2); measuring a frequency (N1, N2) of each of the first and second oscillators; determining by interpolation a corrected frequency measurement (N2C) of the second oscillator (OSC2) depending on a frequency difference measured between the first and second oscillators subjected to the same third control value, on the third control value, and on the control value (S2) applied to the second oscillator; determining by interpolation a new first control value (S1') depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency (NC1); and in applying the new first control value to the first oscillator.
摘要:
The method involves executing multiple loops of an encrypting algorithm on data of an input message, to obtain processed message data results. Each loop is executed by using a different masked key among masked keys until all the masked keys are used once, where the execution of the loop using authentic and dummy keys produces authentic and dummy message data results, respectively. The authentic and dummy data results are stored in respective locations of a memory.
摘要:
A fault detection method for an encryption/decryption system based on a block cipher comprises the steps of subjecting a state array (CST) to multiple rounds, each round comprising a same series of sequential operations transforming the state array; storing the state of a reference operation (ShiftRows) of a current round as a checkpoint state (CHK); storing the state of the reference operation in the next round as an intermediate state; applying one round of reciprocal operations to the intermediate state, starting from the reciprocal of the reference operation (InvShiftRows); and comparing the result state of said one round of reciprocal operations with the checkpoint state.
摘要:
The invention relates to a memory circuit (MEM1) comprising a memory plane (MA) comprising memory cells (MC), and an address decoder (RDEC) configured to apply to the memory plane signals (V 0 -V I-1 , Vsel) for selecting a group of memory cells as a function of an address (AD1). According to the invention, the memory circuit comprises means (LCT) for capturing signals (Vsel) for selecting memory cells appearing in the memory plane, and means (RCOD), for reconstructing, on the basis of the selection signals captured, an address (AD2) of a selected group of memory cells.