公开(公告)号：EP1987520A2

公开(公告)日：2008-11-05

申请号：EP07750961.0

申请日：2007-02-15

申请人： Innovative Silicon SA

发明人： CARMAN, Eric ,  OKHONIN, Serguei ,  JONES, Mark-Eric

IPC分类号： G11C11/34

CPC分类号： H01L29/7841 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/404 ,  G11C11/565 ,  G11C2211/4016

摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)

公开(公告)号：EP1927111A2

公开(公告)日：2008-06-04

申请号：EP06805759.5

申请日：2006-09-19

申请人： Innovative Silicon SA

发明人： BAUSER, Philippe

IPC分类号： G11C11/4099 ,  G11C7/14

CPC分类号： G11C7/14 ,  G11C11/4099

摘要： There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.

公开(公告)号：EP1924997A1

公开(公告)日：2008-05-28

申请号：EP06777170.9

申请日：2006-09-06

申请人： Innovative Silicon SA

发明人： OKHONIN, Serguei ,  NAGOGA, Mikhail

IPC分类号： G11C11/404 ,  G11C11/4076

CPC分类号： G11C11/409 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

公开(公告)号：EP1355316B1

公开(公告)日：2007-02-21

申请号：EP02077116.8

申请日：2002-05-29

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： Fazan, Pierre Christophe ,  Okhonin, Serguei

IPC分类号： G11C11/404

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C2211/4016 ,  G11C2211/4065 ,  G11C2211/4068 ,  H01L2924/15311

公开(公告)号：EP1405314A2

公开(公告)日：2004-04-07

申请号：EP02745383.6

申请日：2002-06-05

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： FAZAN, Pierre, Christophe ,  OKHONIN, Serguei

IPC分类号： G11C11/404 ,  G11C11/403 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

摘要翻译： 公开了一种半导体器件，例如存储器件或辐射检测器，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管， 以及布置在源极和漏极之间用于存储体内产生的电荷的主体。 可以通过施加到晶体管的输入信号来调节主体22中的净电荷的大小，并且可以通过在栅极28与栅极28之间施加电压信号来至少部分地抵消输入信号对净电荷的调节 漏极22以及源极18和漏极22之间。

公开(公告)号：EP1355357A1

公开(公告)日：2003-10-22

申请号：EP02405315.9

申请日：2002-04-18

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： Fazan, Pierre ,  Okhonin, Serguei

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： G11C11/404

摘要： L'invention concerne un dispositif semi-conducteur à mémoire, du type comportant des transistors SOI, formé sur un substrat comprenant :

une plaque de base (12) en matériau semi-conducteur,
une couche isolante (14) disposée sur la plaque de base,
une première couche de matériau semi-conducteur (16), recouvrant la couche isolante (14) et dans laquelle sont formés, par dopage, les sources (18), drains (20) et corps (22) desdits transistors,
un film diélectrique (24) disposé entre la source (18) et le drain (20) de chaque transistor et revêtu d'une couche conductrice formant la grille (26).

Selon l'invention, le dispositif comporte une deuxième couche de matériau semi-conducteur (38) fortement dopé disposée au moins localement en dessous de la première couche (16). Il est ainsi possible de former, dans le corps (22) des transistors, une zone neutre permettant le stockage de charges électriques, même dans des transistors de type FD-SOI.

摘要翻译： 在基板（13）上形成数据存储单元。 每个数据存储单元包括具有源极（18），漏极（22）和栅极（28）的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 体内的净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极以及源极和漏极之间施加电压来防止调节。 包括用于在半导体器件中存储数据的方法的独立权利要求

公开(公告)号：EP1355316A1

公开(公告)日：2003-10-22

申请号：EP02077116.8

申请日：2002-05-29

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： Fazan, Pierre Christophe ,  Okhonin, Serguei

IPC分类号： G11C11/404

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C2211/4016 ,  G11C2211/4065 ,  G11C2211/4068 ,  H01L2924/15311

摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

摘要翻译： 一种数据存储设备：诸如具有数据存储单元的多元性10游离缺失盘DRAM存储器。 每个数据存储单元10具有随时间而变化和darstellt的两个二进制逻辑状态中的一种的物理参数。 选择电路16，写入电路18和清凉电路22施加输入信号提供给数据存储单元通过在使不同变化扭转物理参数的变化与表示二进制逻辑状态中的一个的至少那些细胞的时间 在所述一个小区的物理参数比在其他状态。

公开(公告)号：EP1351307A1

公开(公告)日：2003-10-08

申请号：EP02405247.4

申请日：2002-03-28

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： Fazan, Pierre ,  Okhonin, Serguei

IPC分类号： H01L27/108 ,  G11C11/404

CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L29/7841

摘要： L'invention concerne un procédé de commande d'un dispositif semiconducteur destiné à stocker une charge électrique formée d'un ensemble de particules (24) d'une polarité donnée, comportant un transistor à effet de champ qui comprend un corps (20) à l'intérieur duquel est stockée cette charge.
L'élimination de la charge stockée se fait par recombinaison, dans le corps (20), des particules stockées avec des particules de polarité inverse.

摘要翻译： 在基板（13）上形成数据存储单元。 每个数据存储单元包括具有源极（18），漏极（22）和栅极（28）的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 体内的净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极以及源极和漏极之间施加电压来防止调节。 包括用于在半导体器件中存储数据的方法的独立权利要求

公开(公告)号：EP1671331B1

公开(公告)日：2007-07-11

申请号：EP04787565.3

申请日：2004-09-23

申请人： Innovative Silicon SA

发明人： FAZAN, Pierre ,  OKHONIN, Serguei

IPC分类号： G11C11/404

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： The present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State '0' in a memory cell employing an electrically floating body transistor). In this regard, the present invention programs a logic low or State '0' in the memory cell while the electrically floating body transistor is in the 'OFF' state or substantially 'OFF' state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

公开(公告)号：EP1357603A2

公开(公告)日：2003-10-29

申请号：EP02078585.3

申请日：2002-08-27

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： Fazan, Pierre Christophe ,  Okhonin, Serguei

IPC分类号： H01L29/786 ,  H01L29/788

CPC分类号： H01L29/78696 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/7391 ,  H01L29/7841 ,  H01L29/78648 ,  H01L29/7881

摘要： A semiconductor device such as a DRAM memory device is disclosed. A substrate 12 of semiconductor material is provided with energy band modifying means in the form of a box region 38 and is covered by an insulating layer 14. A semiconductor layer 16 has source 18 and drain 20 regions formed therein to define bodies 22 of respective field effect transistors. The box region 38 is more heavily doped than the adjacent body 22, but less highly doped than the corresponding source 18 and drain 20, and modifies the valence and/or conduction band of the body 22 to increase the amount of electrical charge which can be stored in the body 22.

摘要翻译： 公开了诸如DRAM存储器件的半导体器件。 半导体材料的衬底12具有盒区域38形式的能带修改装置并且被绝缘层14覆盖。半导体层16具有形成在其中的源极18和漏极20区域，以限定各个场的本体22 效应晶体管。 盒区域38比相邻的本体22更重掺杂，但是比相应的源极18和漏极20掺杂程度更低，并且修改本体22的价带和/或导带以增加可以是 存储在主体22中。