摘要:
Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard. The encoding standards can be MPEG-2, MPEG-4, DV-25.
摘要:
Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard. The encoding standards can be MPEG-2, MPEG-4, DV-25.
摘要:
The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.
摘要:
System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a deblocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
摘要:
Aspects of the invention may be found in a method and system for handling out-of-order frames. In one embodiment, a method includes, for example, one or more of the following: receiving an out-of-order frame via a network interface card (NIC)(100); placing data of the out-of-order frame in a host memory (170); and managing information relating to one or more holes in a receive window.
摘要:
Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.
摘要:
There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although the implementation of the technique preferably includes a clipping step, it is performed on the front-end rather than as the last step in the technique, such that the output signal is not a clipped signal. Any noise introduced by the clipping step, so-called clipping noise, is preferably filtered out of the useful frequency band of the signal.
摘要:
Access to secured services may be controlled based on the proximity of a wireless token to a computing device through which access to the secured services is obtained. An authorized user may be provided access to a service only when a wireless token assigned to the user is in the proximity of the computing device. A user's credential may be stored on an RFID token and an RFID reader may be implemented within a security boundary on the computing device. Thus, the credential may be passed to the security boundary without passing through the computing device via software messages or applications. The security boundary may be provided, in part, by incorporating the RFID reader onto the same chip as a cryptographic processing component. Once the information is received by the RFID reader it may be encrypted within the chip. As a result, the information may never be presented in the clear outside of the chip. The cryptographic processing component may cryptographically encrypt/sign the credential received from the token so that assurance may be provided to a service provider that the credentials came from a token that was proximate to the computing device. An RFID reader, cryptographic processing components and a wireless network controller may be implemented on a single chip in a mobile device.