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公开(公告)号：EP4462805A1
公开(公告)日：2024-11-13
申请号：EP23305753.8
申请日：2023-05-12
申请人： NXP B.V.
摘要： A battery management system, comprising: a battery pack enclosure that contains: a master controller and a plurality of slave controllers. Each of the plurality of slave controllers is configured to communicate wirelessly with the master controller using their respective antennas over one of a plurality of wireless channels. The battery management system further comprises: a remote antenna, which is located remote from the master antenna such that it is less shielded by the battery pack enclosure to interference that is external to the battery pack enclosure; and a controller that is configured to: receive signalling from the remote antenna and process the signalling to determine a level of interference in the plurality of wireless channels; and based on the determined level of interference in the plurality of wireless channels, select one of the plurality of wireless channels for wireless communication between the master controller and the plurality of slave controllers.
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公开(公告)号：EP4462681A1
公开(公告)日：2024-11-13
申请号：EP24170810.6
申请日：2024-04-17
申请人： NXP USA, Inc.
IPC分类号： H03K17/12
摘要： A power module may include multiple transistors each respectively having a first current-carrying terminal coupled to a voltage supply, a second current-carrying terminal coupled to an output node, and a control terminal, multiple output driver stages each coupled to the control terminal of a respectively different transistor of the transistors, and a driver module. The driver module may include multiple pre-drivers each coupled to a respectively different output driver stage of the output driver stages and a control module having an input and having multiple outputs coupled to the pre-drivers. The control module may be configured to receive a control signal at the input and to selectively control the pre-drivers to drive at least a subset of the plurality of transistors via the output driver stages based on the control signal.
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公开(公告)号：EP4462676A1
公开(公告)日：2024-11-13
申请号：EP23305752.0
申请日：2023-05-12
申请人： NXP B.V.
发明人： Darthenay,, Frederic
摘要： An amplifier circuit (400) comprising: a first-stage residue-reduction storage unit (408); a final-stage residue-reduction storage unit (409); and a switching network (410). The switching network (410) is operable to control the amplifier circuit (400) according to the following operational configurations: a first residue-reduction configuration; a second residue-reduction configuration; and an operational configuration. Such an amplifier circuit advantageously requires a low number of residue-reduction steps to reduce global residual voltage to a very low level when the amplifier circuit is subsequently used in the operational configuration.
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公开(公告)号：EP4462152A1
公开(公告)日：2024-11-13
申请号：EP24170340.4
申请日：2024-04-15
申请人： NXP B.V.
发明人： Jansen, Feike Guus
摘要： A system includes first and second radar transceivers (100A,100B), a processor (250), and a non-transitory computer-readable medium (180) storing machine instructions. The machine instructions cause the processor (250) to determine a first frequency offset a 1 and a first initial time offset τ initial ;1 between a first clock signal for the first radar transceiver (100A) and a reference clock (260) for the processor (250), and the processor (250) determines a first clock drift for the first clock signal relative to the reference clock (260) based on the frequency offset a 1 and the time offset τ initial;1 . The processor (250) determines a second frequency offset a 2 and a second initial time offset τ initial;2 between a second clock signal for the second radar transceiver (100B) and the reference clock (260), and a second clock drift for the second clock signal relative to the reference clock (260) based on the frequency offset a 2 and the time offset τ initial ;2 . The processor (250) then compensates for the first and second clock drift.
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公开(公告)号：EP4459873A1
公开(公告)日：2024-11-06
申请号：EP23171349.6
申请日：2023-05-03
申请人： NXP USA, Inc.
摘要： The disclosure relates to an integrator circuit (300) for a Sigma-Delta, ΣΔ, modulator, the integrator circuit (300) comprising an integrator module (310) comprising a differential amplifier (301), a sampling module (320) comprising sampling capacitors (CS1p, CS2p, CS1n, CS2n) and a reference module (330) comprising first and second pluralities of reference capacitors (331 1-x , 332 1-x ) connected between respective first and second lines (308, 309) and first and second pluralities of reference switches (331 1-x , 332 1-x ) for connecting each of the reference capacitors (331 1-x , 332 1-x ) to either a first reference terminal (324) or a second reference terminal (325). In operation, the reference switches (331 1-x , 332 1-x ) are switched according to a thermometrically coded quantizer signal.
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公开(公告)号：EP4456512A1
公开(公告)日：2024-10-30
申请号：EP23170592.2
申请日：2023-04-28
申请人： NXP B.V.
摘要： The present invention relates to device for compensating variations in run time of a word of a frame. The invention also relates to a method for the device.
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公开(公告)号：EP4451623A1
公开(公告)日：2024-10-23
申请号：EP23168569.4
申请日：2023-04-18
申请人： NXP B.V.
IPC分类号： H04L12/417
摘要： The invention relates to a CAN controller module. The CAN controller module is configured to detect transmission errors during transmissions of bits of a CAN frame via a CAN but and to handle these transmission errors robustly such that a high transmission rate is possible even if the transmission errors occur. The invention also relates to a method for the CAN controller module.
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公开(公告)号：EP4002702B1
公开(公告)日：2024-10-02
申请号：EP20209015.5
申请日：2020-11-20
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公开(公告)号：EP4249873B1
公开(公告)日：2024-09-25
申请号：EP22305340.6
申请日：2022-03-22
CPC分类号： G01K15/005 , G01K7/01
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公开(公告)号：EP3859892B1
公开(公告)日：2024-09-18
申请号：EP20154941.7
申请日：2020-01-31
CPC分类号： H01Q3/267 , H01L23/66 , G01R1/045 , G01R31/2822 , H04B17/14 , G01S7/4082 , G01S7/4017 , G01S7/028 , G01S13/931 , H01L2223/667720130101 , H01L2223/662720130101 , H01L2224/1622520130101 , H01L2224/13120130101
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