利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

202 条记录 (耗时 0.018 秒)

    OPEN LOOP LOAD PULL ARRANGEMENT WITH DETERMINATION OF INJECTIONS SIGNALS
    1.
    发明授权
    OPEN LOOP LOAD PULL ARRANGEMENT WITH DETERMINATION OF INJECTIONS SIGNALS 有权

    公开(公告)号：EP2279423B1

    公开(公告)日：2018-08-08

    申请号：EP09735073.0

    申请日：2009-04-01

    申请人： Anteverta-MW B.V.

    发明人： MARCHETTI, Mauro ,  PELK, Marco Johannes ,  DE VREEDE, Leonardus Cornelis Nicolaas

    IPC分类号： G01R27/32 ,  G01R31/28

    CPC分类号： G01R27/32 ,  G01R31/2822

    摘要： Measurement arrangement and method for active load pull measurements of a device under test (1). A wideband analog-to-digital conversion block (3) is provided for obtaining measurement data. First and second injection signal generators (7, 8) are connected to a source side and a load side of the device under test (1). This set up allows to create predetermined reflection coefficients at reference planes of the device under test (1). Injection signal parameters as determined are converted into the injection signals at the source and load side by digital-to-analog conversion. The wideband analog-to-digital conversion block (3) is further arranged for analog-to-digital conversion of the intermediate frequency signals to obtain the actual measured reflection coefficient versus frequency functions with a first frequency resolution. The first frequency resolution applied in the analog-to-digital conversion is equal to or better than a second frequency resolution applied in the digital-to-analog conversion.

    CONFIGURABLE BIAS TEE
    2.
    发明公开
    CONFIGURABLE BIAS TEE 审中-公开
    可配置的偏置TEE

    公开(公告)号：EP2921869A2

    公开(公告)日：2015-09-23

    申请号：EP15159817.4

    申请日：2015-03-19

    申请人： Keithley Instruments, Inc.

    发明人： Sobolewski, Gregory

    IPC分类号： G01R31/28

    CPC分类号： H03H7/465 ,  G01R19/00 ,  G01R19/0015 ,  G01R27/025 ,  G01R31/2822 ,  G01R31/2889 ,  H01P1/2007 ,  H01P5/00 ,  H03H7/0123 ,  H03H7/46

    摘要： Bias tees, according to certain embodiments of the present invention, include switches (645, 650) in the AC signal path, the DC signal path, or both, to improve the capability of the bias tees to be used for high impedance AC measurement, low current DC measurement, or both. Optical control (670, 675) of the switches, as well as control of the switches using a DC bias present within the AC signal input to the bias tee, is described. Including a set of diodes into the DC signal path, rather than a switch, provides enhanced capability of the bias tee to be used for high impedance AC measurements.

    摘要翻译： 根据本发明的某些实施例，偏置T形开关包括AC信号路径，DC信号路径或两者中的开关（645,650），以改善偏置T形件用于高阻抗AC测量的能力， 低电流直流测量或两者兼而有之。 描述开关的光学控制（670,675）以及使用存在于输入到偏置T形件的AC信号内的DC偏压来控制开关。 将一组二极管包含在直流信号路径中而不是开关中，可以提高偏置三通的高阻抗交流测量能力。

    Circuit and method for detection of IC connection failure
    4.
    发明公开
    Circuit and method for detection of IC connection failure 有权
    Schaltung und Verfahren zur Erkennung von IC-Verbindungsstörungen

    公开(公告)号：EP2866040A1

    公开(公告)日：2015-04-29

    申请号：EP13189631.8

    申请日：2013-10-22

    申请人： NXP B.V.

    发明人： Vaucher, Cicero, Silveira ,  Huang, Mingda ,  De Graauw, Antonius

    IPC分类号： G01R31/04 ,  G01R31/28 ,  G01R31/00

    CPC分类号： G01R31/02 ,  G01R31/006 ,  G01R31/048 ,  G01R31/2822

    摘要： The invention provides a testing circuit for testing a connection between a chip and external circuitry. A current source is used to inject a DC current towards the connection to be tested from the chip side. On-chip ESD protection is provided giving a path between the connection to be tested and a fixed voltage line. A shunt path is also coupled to the connection to be tested on the external circuitry side. It is determined if the current source current flows through the ESD protection circuit, and this can be used to determine whether or not the connection to be tested presents an open circuit for the DC test current.

    摘要翻译： 本发明提供了一种用于测试芯片和外部电路之间的连接的测试电路。 电流源用于向芯片侧的待测连接注入直流电流。 提供片上ESD保护，提供要测试的连接和固定电压线之间的路径。 并联路径也耦合到要在外部电路侧进行测试的连接。 确定电流源电流是否流过ESD保护电路，这可以用于确定待测试的连接是否为DC测试电流提供开路。

    Bit error pattern analyzer and method
    7.
    发明公开
    Bit error pattern analyzer and method 审中-公开
    位错误模式分析仪和方法

    公开(公告)号：EP2775652A2

    公开(公告)日：2014-09-10

    申请号：EP14158335.1

    申请日：2014-03-07

    申请人： JDSU Deutschland GmbH

    发明人： Schnizler, Reiner ,  Brooks, Paul

    IPC分类号： H04L1/20

    CPC分类号： H04L1/241 ,  G01R31/2822 ,  G01R31/2839 ,  G06F7/58 ,  H04L1/20 ,  H04L1/244 ,  H04L25/064

    摘要： The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

    摘要翻译： 用于测试数据链路的方法和设备 通过数据链路发送一个或多个PRBS信号的单通道或多通道误码测试仪增加了一个原始误码缓冲器，用于存储每个检测到的误码事件的误码信息和一个误码模式分析器。 识别最频繁出现的车道内误码模式，车道间误码模式和位打滑模式，并分析它们的特性，以提供指示检测到的误码和误码的根本原因的信息。

    High frequency circuit module with stripline divider
    8.
    发明公开
    High frequency circuit module with stripline divider 有权
    高频电路模块与带状线分布

    公开(公告)号：EP2197073A3

    公开(公告)日：2012-09-26

    申请号：EP09252612.8

    申请日：2009-11-13

    申请人： Hosiden Corporation

    发明人： Kondo, Hayato ,  Maeda, Kenji

    IPC分类号： H01P5/12 ,  G01R31/28

    CPC分类号： H01P5/12 ,  G01R31/2822 ,  H05K1/0243

    摘要： Top face of circuit board 30 is provided with electrode pads 313a to 313j for mounting a multi-pin connector 10; its back face is provided with microstrip lines 334a to 334j for electrically connecting the multi-pin connector 10 with coaxial connectors 20a to 20j. Circuit board 30 has a ground pattern 333 serving as a counter-electrode of microstrip lines 334a to 334j. The routing directions β1 of adjacent microstrip lines 334d and 334e, 334f and 334g, 334h and 334i are opposite each other. Through-hole electrodes 34a to 34j for establishing electrical connection between electrode pads 313a to 313j and microstrip lines 334a to 334j are disposed within a component mounting area γ, i.e., below the multi-pin connector 10.
    The invention aims to reduce crosstalk in an evaluation board for measurement of high frequency characteristics of transmission paths including a multi-pin connector and reduce the influence of impedance of the multi-pin connector on the evaluation board.

    KONTAKTLOSES MESSSYSTEM
    10.
    发明授权
    KONTAKTLOSES MESSSYSTEM 有权
    非接触式测量系统

    公开(公告)号：EP2174151B1

    公开(公告)日：2011-10-26

    申请号：EP08785051.7

    申请日：2008-07-24

    申请人： Rosenberger Hochfrequenztechnik GmbH & Co. KG

    发明人： ZELDER, Thomas

    IPC分类号： G01R31/304

    CPC分类号： G01R1/07 ,  G01R1/24 ,  G01R27/32 ,  G01R31/2822 ,  G01R31/312 ,  G01R31/315 ,  G01R35/005

    摘要： The invention relates to a contactless measuring system having at least one test prod (28) forming part of a coupling structure for the contactless decoupling of a signal running on a signal waveguide (26), wherein the signal waveguide (26) is designed as a conductor of the electric circuit on a circuit board (24) and as part of an electric circuit (52). To this end, at least one contact structure (18; 44) is configured and disposed on the circuit board (24) such that said contact structure (18; 44) is galvanically separated from the signal waveguide (26), forms part of the coupling structure, is displaced completely within the near field of the signal waveguide (26), and has at least one contact point (42), which may be electrically contacted by a contact of the test prod (28).