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1.发明公开
公开(公告)号：EP4459853A1
公开(公告)日：2024-11-06
申请号：EP24166256.8
申请日：2024-03-26
摘要： The present disclosure provides a bidirectional power supply (100) includes an AC port (110), a line-frequency rectifier/inverter (120) and a set of switches (215). A bidirectional resonant supply (100) is coupled to a DC port (140) with primary-side switches (240) and secondary-side switches (250) respectively arranged on a primary and secondary side of a transformer (225). A controller (150) controls the primary-side switches (240) and the secondary-side switches (250) by controlling switching frequency based on a determined value while setting time delay between control of the primary-side (240) and the secondary-side switches (250) to be a predefined time delay or by controlling the time delay between control of the primary-side (240) and the secondary-side switches (250) based on a determined value while setting the switching frequency to be a predefined switching frequency.
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公开(公告)号：EP4456400A1
公开(公告)日：2024-10-30
申请号：EP23192594.2
申请日：2023-08-22
摘要： A power converter (1) is provided. The power converter (1) includes first to fourth switches (SW1, SW2, SW3, SW4) electrically connected in series, a flying capacitor (Cf) and a controller (11). Positive and negative terminals of the flying capacitor (Cf) are electrically connected to the second and third switches (SW2, SW3) respectively. The controller (11) operates the first and fourth switches (SW1, SW4) to perform a first complementary switching with a first dead time, and operates the second and third switches (SW2, SW3) to perform a second complementary switching with a second dead time. The controller (11) determines to regulate the first or second dead time by detecting a capacitor voltage (Vf) of the flying capacitor (Cf), such that the capacitor voltage (Vf) of the flying capacitor (Cf) is maintained within a balance voltage range.
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公开(公告)号：EP4447630A1
公开(公告)日：2024-10-16
申请号：EP24163400.5
申请日：2024-03-13
发明人： Li, Yi-Syuan , Ajitha, , Hsu, Ching-Chuan
IPC分类号： H05K7/20
摘要： A power-supply-unit assembly structure (1) is disclosed and includes a housing base (10), a cover (30) and a PSU. The housing base (10) includes two opposite ending walls (11, 12) and two lateral walls (13a, 13b) disposed around a bottom plate (14) to form an accommodation for accommodating a main body (40) of the PSU, and coved by the cover (30). A ventilation inlet (21) and a ventilation outlet (22) passing through the two lateral walls (13a, 13b) are disposed adjacent to the two opposite ending walls (11, 12), respectively, and in communication with each other through circuitous paths formed through retaining walls (15, 16). The PSU includes a fan (42) configured to drive an airflow transported along the circuitous paths, so that the heat dissipation performance is enhanced, a water-repellent structure is provided, and the protection and the portability are improved.
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公开(公告)号：EP4406483A3
公开(公告)日：2024-10-09
申请号：EP24181103.3
申请日：2021-03-24
发明人： Chen, Sih-Yu , Lee, Jhih-Shian , Chen, Ya-Chen
CPC分类号： A61B6/032 , A61B6/037 , A61B6/5288 , A61B6/5264 , A61B6/5217 , A61B6/469 , G06T11/00
摘要： A method for gating in tomographic imaging system includes steps of: (a) performing a tomographic imaging on an object with a target moving periodically along a first axis (s) for acquiring projection images (Pθts); (b) obtaining projected curves (Cθts) by summing up pixel values along a direction of a second axis (t) perpendicular to the first axis (s) in each projection image (Pθts); (c) determining a target zone on the projection images (Pθts), wherein a central position on the first axis (s) of the target zone is corresponding to a position having the largest variation in the projected curves (Cθts) on the first axis (s); (d) calculating parameter values of pixel values in the target zones and obtaining a curve of a moving cycle of the target according to the parameter values; and (e) selecting the projection images (Pθts) under the same state in the moving cycle for image reconstruction according to the curve of the moving cycle of the target.
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公开(公告)号：EP4429087A1
公开(公告)日：2024-09-11
申请号：EP23189915.4
申请日：2023-08-07
发明人： HUNG, Hsien-Feng , SHEN, Cheng-Yu , YANG, Chung-Han , LIN, Quan-Sheng , CHEN, Yi , MA, Cong-Xiang
IPC分类号： H02K11/33
CPC分类号： H02K11/33
摘要： An electric motor (100) includes a motor main body (110) and an inverter (120). The inverter (120) is axially stacked on one end of the motor main body (110), and the inverter (120) includes a gate driver, a control circuit (122), a capacitor module (220), a DC bus bar (160), a plurality of power modules (126) and a plurality of AC bus bars (124). The power module includes a plurality of AC output terminals (127), a plurality of DC input terminals (204) and a plurality of signal terminals (232, 242, 252), and the AC bus bars (124) are respectively connected to corresponding AC output terminals (127) and extend downward to a motor coil of the motor main body (110). The power modules (126) and the corresponding DC input terminals (204) are annularly arranged around the capacitor module (220), the DC bus bar (160) is extended and electrically connected to the corresponding DC input terminals (204) and the capacitor module (220).
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公开(公告)号：EP4418517A1
公开(公告)日：2024-08-21
申请号：EP23177904.2
申请日：2023-06-07
CPC分类号： H02M1/0058 , H02M1/4233 , H02M1/4241 , H02M1/346
摘要： A Totem-pole power factor corrector receives an input power source (Vin) and convert the input power source (Vin) into an output power source (Vo). The Totem-pole power factor corrector includes an input inductor (L, Lboost, nL), a fast-switching switch leg (11), a slow-switching switch leg (12), a resonant tank (13), and an output capacitor (Co). The fast-switching switch leg (11) includes a fast-switching upper switch (S2, nS2) and a fast-switching lower switch (S1, nS1), and the fast-switching upper switch (S2, nS2) and the fast-switching lower switch (S1, nS1) are commonly coupled at a first middle node (N1). The slow-switching switch leg (12) is coupled in parallel to the fast-switching switch leg (11), and the slow-switching switch leg (12) includes a slow-switching upper and a slow-switching lower switch (Mi). The resonant tank (13) includes a resonant inductor (Lr, nLr) and at least one resonant capacitor (Cr, nCr). A first end of the resonant inductor (Lr, nLr) is coupled to the first middle node (N1), and a second end of the resonant inductor (Lr, nLr) is coupled to the at least one capacitor.
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公开(公告)号：EP4369363A3
公开(公告)日：2024-07-10
申请号：EP23209405.2
申请日：2023-11-13
发明人： CHANG, Yi-Sheng
CPC分类号： H02M3/158 , H02M3/1582 , H02M3/33523 , H02M3/335 , H02M1/4225 , H02M1/0064 , H02J1/082 , H02M3/003 , H01F2027/280920130101 , H01F27/40 , H01F2027/281920130101 , H01F27/2804 , H01F2027/40820130101 , H01F27/346 , H01F2027/34820130101
摘要： A planar transformer (2B) is applied to an isolated converter (400), and the isolated converter (400) includes a primary-side circuit (1B) and a secondary-side circuit (3B). The planar transformer (2B) includes a circuit board (CB2) and an iron core (C2), and the circuit board (CB2) includes a primary-side layer (LP) and a secondary-side layer (LS). The circuit board (CB2) is arranged in the isolated converter (400), and the primary-side layer (LP) and the secondary-side layer (LS) include a primary-side trace (Tp2) and a secondary-side trace (Ts2) respectively. The primary-side trace (Tp2) is formed on the primary-side layer (LP) and serves as a primary-side coil (22B) coupled to the primary-side circuit (1B). The secondary-side trace (Ts2) is formed on the secondary-side layer (LS) and serves as a secondary-side coil (24B) coupled to the secondary-side circuit (3B). The iron core (C2) includes a core pillar (C22), the core pillar (C22) penetrates a through hole (H4) of the circuit board (CB2), and the primary-side trace (Tp2) and the secondary-side trace (Ts2) surround the through hole (H4).
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公开(公告)号：EP4369586A1
公开(公告)日：2024-05-15
申请号：EP23209486.2
申请日：2023-11-13
发明人： CHANG, Yi-Sheng , HSU, Cheng-Chan , CHU, Chia-Wei , YANG, Chun-Yu , HUANG, Deng-Cyun , CHIU, Yi-Hsun , LAI, Chien-An , WANG, Yu-Tai , HO, Chi-Shou , WU, Zhi-Yuan , LU, Ko-Wen
CPC分类号： H02M3/158 , H02M3/1582 , H02M3/33523 , H02M3/335 , H02M1/4225 , H02M1/0064 , G06F1/189 , H02J1/082 , H02M3/003 , H01F2027/280920130101 , H01F27/40 , H01F2027/281920130101 , H01F27/2804 , H01F2027/40820130101 , H01F27/346 , H01F2027/34820130101
摘要： A power supply unit (PSU) supplies power to a load, and the power supply unit (PSU) includes a power factor corrector (PFC), a DC conversion module (CR_DC), and an isolated conversion module (CR_M). The power factor corrector (PFC) is plugged into a first main circuit board (CB_M1) and converts an AC power into a DC power. The DC conversion module (CR_DC) is plugged into the first main circuit board (CB_M1) and converts the DC power into a main power. The isolated conversion module (CR_M) includes a bus capacitor (Cbus), the bus capacitor (Cbus) is coupled to the DC conversion module (CR_DC) through a first power copper bar (BR_P1), and coupled to the power factor corrector (PFC) through a second power copper bar (BR_P2). The first power copper bar (BR_P1) and the second power copper bar (BR_P2) are arranged on a side opposite to the first main circuit board (CB_M1), and are arranged in parallel with the first main circuit board (CB_M1).
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公开(公告)号：EP4369580A1
公开(公告)日：2024-05-15
申请号：EP23206410.5
申请日：2023-10-27
CPC分类号： H02M1/0095 , H02M1/0058 , H02M1/4216 , H02M1/4233 , H02M7/4837 , H02M7/4833 , H02M7/5388
摘要： FCML rectifiers and control methods thereof are provided. The FCML rectifier operates with an input voltage (vin) and includes an inductor (L), a plurality of upper switches (S1, S2, S3 ..., SN), and a plurality of lower switches (S1, S2, S3..., SN). The upper and lower switches are electrically connected in series. The inductor (L) is coupled between the input voltage (vin) and a midpoint between the upper switches (S1, S2, S3 ..., SN) and the lower switches (S1, S2, S3..., SN). During critical transition points, at least one of first and second modulation schemes is performed. In the first modulation scheme, any rising edge of the control signal of any one lower switch (S1, S2, S3..., SN) is controlled to be synchronous with a rising edge of the control signal of at least one another lower switch (S1, S2, S3..., SN) for achieving ZVS. In the second modulation scheme, a phase-shift (Ø) of the control signals and a switching frequency (fs) are controlled to achieve ZVS with minimum conduction loss.
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公开(公告)号：EP4369565A1
公开(公告)日：2024-05-15
申请号：EP23171080.7
申请日：2023-05-02
发明人： CHEN, Si-Wei , KUO, Wen-Hao
IPC分类号： H02J7/06
CPC分类号： H02J2207/5020200101 , H02J7/00712 , H02J7/06
摘要： A charging circuitry (10A) includes a power electronic converter (13), a current sensor (14), a voltage boost/buck controller (15) and a charging mode controller (16). The power electronic converter (13) is configured to charge or discharge a supercapacitor (12) according to a control command (CTRL). The current sensor (14) is coupled to the supercapacitor (12) for detecting a first sensed voltage (ISENSE+) and a second sensed voltage (ISENSE-). The voltage boost/buck controller (15) is configured to generate the control command (CTRL) and a current command (IMON_OUT) according to the first (ISENSE+) and second sensed voltages (ISENSE-) and an overall feedback (FB_OUT). The charging mode controller (16) is configured to generate a current feedback (FB1) and a voltage feedback (FB2) to the voltage boost/buck controller (15) according to a driving voltage (CV), the current command (IMON_OUT) and a third sensed voltage (VSENSE) of the supercapacitor (12). The third sensed voltage (VSENSE), the current feedback (FB1) and the voltage feedback (FB2) are superposed as the overall feedback (FB_OUT) and then inputted to the same input terminal of the voltage boost/buck controller (15).
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