PROVIDING AN INTERFACE FOR AN AVIONICS DATA TRANSFER SYSTEM

    公开(公告)号:EP4404072A2

    公开(公告)日:2024-07-24

    申请号:EP24177051.0

    申请日:2017-01-06

    IPC分类号: G06F13/38

    CPC分类号: G06F13/385

    摘要: Systems and methods 500 for providing an efficient and configurable port interface in an avionics data transfer system 100 are provided. For instance, in one embodiment a set of virtual ports associated with an avionics data transfer system 100 can be defined. At least as a subset of the virtual ports can be mapped to one or more addresses 402 in a memory space associated with the data transfer system 100, such that each virtual port has a fixed definition in the memory space. One or more of the virtual ports can then be associated with one or more physical ports 308 associated with an interface between a host computing device 202 and an end system 200 in the data transfer system 100 by specifying for the one or more virtual ports a plurality of port parameters that define the respective one or more physical ports 308.

    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FORMING

    公开(公告)号:EP4216265A3

    公开(公告)日:2023-09-06

    申请号:EP23151822.6

    申请日:2023-01-16

    摘要: A semiconductor device package (100), (200) comprises a semiconductor switching device (12) having a body (13), the body (13) including a first side (13a), and a second side (13b) opposing the first side (13a) coupled to a substrate (14). A gate terminal (35) is defined on the semiconductor switching device first side (13a), the gate terminal (35) having a first side (35a), and a second side (35b) opposing the first side (35a) and facing the body (13). A first gate resistor (15) is disposed on the gate terminal first side (35a), and coupled electrically in series with the gate terminal (35).

    METHOD AND SYSTEM FOR DATA TRANSFER ON AN AVIONICS BUS

    公开(公告)号:EP4236268A2

    公开(公告)日:2023-08-30

    申请号:EP23180951.8

    申请日:2020-10-23

    IPC分类号: H04L69/00

    摘要: A method (500) for transmitting a set of conforming data frames (52) in a specialized data network (50), the method comprising generating (502) a specialized header (54), providing (504) the specialized header (54) to a data destination (20), generating (506) a set of conforming data frames (72), providing (508) at least a subset of the conforming data frames (72) to the data destination (20), identifying (510) the subset (S1, S2, S3, S4, S5) of conforming data frames (72), and performing (512) processing operations on the stored subset (S1, S2, S3, S4, S5) of conforming data frames (72).

    PROCESSOR VIRTUALIZATION IN UNMANNED VEHICLES

    公开(公告)号:EP4220326A2

    公开(公告)日:2023-08-02

    申请号:EP23160843.1

    申请日:2019-01-04

    IPC分类号: G05D1/00 G06F9/455

    摘要: A processing system for an unmanned vehicle (UV) such as an unmanned aerial vehicle (UAV) is provided. The processing system comprises a first processing unit of an integrated circuit and a second processing unit of the integrated circuit. The processing system comprises a first operating system 802 provisioned using the first processing unit. The first operating system 802 is configured to execute a first vehicle control process. The processing system comprises a virtualization layer 807 configured using at least the second processing unit, and a second operating system 836 provisioned using the virtualization layer 807. The second operating system 836, 844 is configured to execute a second vehicle control process.

    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FORMING

    公开(公告)号:EP4216265A2

    公开(公告)日:2023-07-26

    申请号:EP23151822.6

    申请日:2023-01-16

    摘要: A semiconductor device package (100), (200) comprises a semiconductor switching device (12) having a body (13), the body (13) including a first side (13a), and a second side (13b) opposing the first side (13a) coupled to a substrate (14). A gate terminal (35) is defined on the semiconductor switching device first side (13a), the gate terminal (35) having a first side (35a), and a second side (35b) opposing the first side (35a) and facing the body (13). A first gate resistor (15) is disposed on the gate terminal first side (35a), and coupled electrically in series with the gate terminal (35).