公开(公告)号：EP2363886A1

公开(公告)日：2011-09-07

申请号：EP10195783.5

申请日：2010-12-17

申请人： S.O.I. Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

摘要： The invention relates, according to a first aspect, to a data path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator substrate comprising a thin layer of semiconductor material separated from a bulk substrate by an insulating layer, the cell comprising an array of field-effect transistors, each transistor having, in the thin layer, a source region (S 7 ), a drain region (D 7 ) and a channel region (C 7 ) which is bounded by the source and drain regions, and further including a front gate control region (GA 7 ) formed above the channel region, characterized in that at least one transistor (T 7 ) has a back gate control region (GN 2 ) formed in the bulk substrate beneath the channel region, the back gate region being able to be biased so as to modify the performance characteristics of the transistor.

摘要翻译： 本发明涉及，雅鼎的第一方面，涉及一种数据通路单元具体angepasst其对使用环境中对包括在绝缘通过从体衬底分开的半导体材料的薄层的半导体绝缘体上的基板产生的集成电路 层，其由限定的细胞，其包含场效应晶体管的阵列，其具有，在薄层，源极区（S 7），漏极区（D 7）和沟道区中的每个晶体管（C 7）所有 源和漏区，并且还包括在所述沟道区之上形成的前栅极控制区（GA 7），在其特点做至少一个晶体管（T 7）具有背栅控制区域在本体的基体构成的下方（GN 2） 沟道区域中，能够在背栅区被偏置以改变晶体管的性能特性。

公开(公告)号：EP1483793B1

公开(公告)日：2011-08-31

申请号：EP03727583.1

申请日：2003-03-12

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  S.O.I. Tec Silicon on Insulator Technologies

发明人： TEMPLIER, François ,  BILLON, Thierry ,  DAVAL, Nicolas

IPC分类号： H01L29/872

CPC分类号： H01L29/6606 ,  H01L21/0475 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/78684 ,  H01L29/8126 ,  H01L29/872 ,  Y10S438/931

摘要： The invention relates to a power junction device comprising: a SiCOI-type substrate with a silicon carbide layer (16) which is insulated from a solid support (12) by means of an insulating buried layer (14), and at least one Schottky contact between a first metallic layer (40) and the silicon carbide surface layer (16), said first metallic layer (30) forming an anode.

公开(公告)号：EP2339615A1

公开(公告)日：2011-06-29

申请号：EP10192594.9

申请日：2010-11-25

申请人： S.O.I. Tec Silicon on Insulator Technologies

发明人： Vaufredaz, Alexandre

IPC分类号： H01L21/762

CPC分类号： H01L21/76256

摘要： Procédé de réalisation d'une hétérostructure comprenant une étape de collage (S5) d'une première plaque (110) sur une deuxième plaque (120), la première plaque (110) ayant un coefficient de dilatation thermique inférieur au coefficient de dilatation thermique de la deuxième plaque (120) et au moins une étape de recuit de renforcement de collage (S7). Le procédé est notamment caractérisé en ce qu 'il comprend, après l'étape de collage (S5) et avant l'étape de recuit de renforcement de collage (S7), au moins une étape de détourage au moins partiel (S5) de la première plaque (110).

摘要翻译： 该方法包括将晶片（110）（即硅或硅绝缘体（SOI））衬底接合到另一晶片（120）即蓝宝石衬底上，其中前晶片的热膨胀系数低于后者的热膨胀系数 晶圆。 前一个晶片被部分地修整，使得前一个晶片在前晶片的修整部分的水平处具有低于或等于55微米的厚度。 对晶片的结合进行加强退火。 在接合步骤之后和退火步骤之前进行修整步骤。

公开(公告)号：EP2037288B1

公开(公告)日：2011-06-22

申请号：EP07291091.2

申请日：2007-09-11

申请人： S.O.I. TEC Silicon on Insulator Technologies

发明人： Allibert, Frederic ,  Kononchuk, Oleg

IPC分类号： G01R31/265 ,  H01L21/66

CPC分类号： G01R31/2656 ,  G01R31/2648

公开(公告)号：EP2333833A1

公开(公告)日：2011-06-15

申请号：EP10192766.3

申请日：2010-11-26

申请人： S.O.I. Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard

IPC分类号： H01L27/12 ,  H01L27/118 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11807

摘要： The invention relates, according to a first aspect, to a semiconductor device formed on a semiconductor-on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating film, the device comprising an array of patterns each formed from at least one field-effect transistor, each transistor having, in the thin film, a source region, a drain region and a channel region which is delimited by the source and drain regions, and furthermore comprising a front control gate region formed above the channel region, the patterns being arranged in the form of rows, the source and drain regions of any one row having the same dimensions and being spaced apart by front control gate regions of fixed dimensions, characterized in that at least one transistor of a pattern has a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate.

摘要翻译： 本发明涉及，雅丁第一个方面，为了在绝缘电影形成在包括通过从一个基底基板分离的半导体材料的薄膜的半导体绝缘体上的基板的半导体器件，其包括图案阵列的装置中的各从形成 至少一个场效应晶体管，其每一个由所述源和漏区分隔，进一步包括在沟道上方形成的前控制栅极区的晶体管具有，在薄膜，源区，漏区和沟道区的所有 区域，图案被排列成行的形式，其具有相同的尺寸和由固定尺寸的前控制栅区，其特征在于在间隔开任意一行的源极和漏极区并一个图案中的至少一个晶体管具有 在沟道区之下的基础衬底FORMED背控制栅区，能够的背栅区被偏置以移动T的阈值电压 他晶体管以模拟晶体管的沟道宽度的修改或迫使晶体管保持关闭或打开的任何施加电压在其前控制栅极。

公开(公告)号：EP2256798A1

公开(公告)日：2010-12-01

申请号：EP10177181.4

申请日：2007-07-12

申请人： S.O.I. Tec Silicon on Insulator Technologies

发明人： Neyret, Eric ,  Kerdiles, Sébastien

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： L'invention concerne un procédé de réalisation d'une structure comprenant une couche mince de matériau semi-conducteur sur un substrat, comportant les étapes de:
- création d'une zone de fragilisation dans l'épaisseur du substrat donneur;
- collage du substrat donneur avec un substrat support ;
- détachement du substrat donneur au niveau de la zone de fragilisation, pour transférer une partie du substrat donneur sur le substrat support et former la couche mince sur celui-ci ;
- traitement thermique de la structure obtenue après détachement pour stabiliser l'interface de collage entre la couche mince et le substrat support, réalisé de manière à éviter l'apparition de lignes de glissement dans la couche mince.

摘要翻译： 该方法包括在施主衬底的厚度上产生脆化区域，并将施主衬底粘合到支撑衬底上。 施主衬底在脆化区域处被分离，以将支承衬底上的一部分施主衬底转移到支撑衬底上并在支撑衬底上形成半导体结构的薄层。 接合界面，例如 通过进行快速热退火操作来稳定在薄层和支撑衬底之间限定的氧化物/硅界面。

公开(公告)号：EP2203932A1

公开(公告)日：2010-07-07

申请号：EP08804589.3

申请日：2008-09-23

申请人： S.O.I. TEC Silicon on Insulator Technologies

发明人： ABIR, Hocine ,  LANGER, Robert

IPC分类号： H01L21/20 ,  H01L21/26 ,  H01L21/324 ,  H01L21/762 ,  H01L21/205 ,  C30B25/02

CPC分类号： H01L21/76254 ,  H01L23/36 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a method of fabricating a structure (1) for electronics, optics, optoelectronics or photovoltaics, the structure (1) comprising a substrate (10) and a layer (20) formed by depositing a material on one of the faces of the substrate (10), this method being characterized in that it comprises the steps of : - formation of a embrittled substrate comprising a embrittlement zone defining, on the one hand, said substrate (10) and, on the other hand, a remainder, - deposition of a layer (20,21) of said material on each one of the two faces of the embrittled substrate, - cleavage of the embrittled substrate, so as to form the structure (1) in which face (IB) of the substrate (10) is covered with the layer (20) of the material deposited while its other face (IA) is exposed.

公开(公告)号：EP2164097A2

公开(公告)日：2010-03-17

申请号：EP09178893.5

申请日：2003-07-16

申请人： S.O.I. Tec Silicon on Insulator Technologies

发明人： Ghyselen, Bruno

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/76259

摘要： The invention provides a method of smoothing the outline of a useful layer (66) of material transferred to a support substrate (7), said method comprising at least one step of molecular bonding the front face (600) of a source substrate (6) to the receiving face (700) of a support substrate (7), and a step of transferring a useful layer (66) deriving from said source substrate (6) onto said support substrate (7). This method is characterized in that prior to said bonding step, at least one of the faces selected from said front face (600) and said receiving face (700) undergoes a machining operation intended to form a shoulder (61) over at least a portion of its periphery, said shoulder (61) defining an inner projecting zone (62) the top face (620) of regular outline (C" 6 ) so that after bonding, said useful layer (66) is transferred to said support substrate (7) with a regular outline.
Application to the fabrication of a composite substrate for optics, electronics or optoelectronics.

摘要翻译： 本发明提供了一种平滑转移到支撑衬底（7）的材料的有用层（66）的轮廓的方法，所述方法包括至少一个将源衬底（6）的前表面（600）分子结合的步骤， 到支撑衬底（7）的接收面（700）的步骤，以及将源自所述源衬底（6）的有用层（66）转移到所述支撑衬底（7）上的步骤。 该方法的特征在于，在所述结合步骤之前，从所述前面（600）和所述接收面（700）中选择的面中的至少一个面进行旨在形成肩部（61）的机加工操作，所述肩部 ，所述肩部（61）限定具有规则轮廓（C“6）的顶面（620）的内部突出区域（62），使得在结合之后，所述有用层（66）被转移到所述支撑衬底 ），具有规则的轮廓。适用于制造光学，电子或光电子复合基板。

公开(公告)号：EP2137755A2

公开(公告)日：2009-12-30

申请号：EP08719275.3

申请日：2008-02-26

申请人： S.O.I. TEC Silicon on Insulator Technologies

发明人： BOURDELLE, Konstantin

IPC分类号： H01L21/18 ,  H01L21/265

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L21/2007

摘要： The invention relates to a method of fabricating a hybrid substrate comprising at least two layers of crystalline material that are bonded directly to each other. This method is noteworthy in that it comprises steps consisting in: implanting at least one category of atomic and/or ionic species into a donor substrate so as to form therein a weakened zone forming the boundary between an active layer and a remainder; subjecting the front faces of the donor substrate and of a receiver substrate, to a heat treatment between 900°C and 1200°C, under hydrogen and/or argon for a time of at least 30 seconds; bonding said front faces to each other; detaching said remainder; the nature, implantation dose and implantation energy of said species being chosen so that the defects induced by these species within the donor substrate allow the remainder of the donor substrate to be subsequently detached but do not develop sufficiently during said heat treatment to prevent the subsequent bonding or to deform the front face of the donor substrate.

公开(公告)号：EP2109883A1

公开(公告)日：2009-10-21

申请号：EP07734269.9

申请日：2007-02-08

申请人： S.O.I. TEC Silicon on Insulator Technologies

发明人： KONONCHUK, Oleg ,  LETERTRE, Fabrice ,  LANGER, Robert

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions, the structure comprising a support substrate, a top layer and an oxide layer between the support substrate and the top layer, the method comprising the steps of: a) providing a top layer made of a crystalline material, b) bonding the top layer with a support substrate made of a polycrystalline material having high heat dissipation properties, such that an oxide layer is formed at the bonding interface, in order to obtain said structure, characterized in that it further comprises a heat treatment of the structure in an inert or reducing atmosphere at a predetermined temperature and a predetermined duration to increase the heat dissipation properties by dissolving at least a part of the oxide layer.