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    STANDARD CELL FOR VERTICAL TRANSISTORS
    1.
    发明公开
    STANDARD CELL FOR VERTICAL TRANSISTORS 审中-公开

    公开(公告)号：EP3343614A3

    公开(公告)日：2018-10-31

    申请号：EP17210357.4

    申请日：2017-12-22

    申请人： IMEC vzw ,  Vrije Universiteit Brussel

    发明人： RYCKAERT, Julien ,  HUYHN BAO, Trong

    IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2027/11816 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

    摘要： A standard cell semiconductor device (1) is disclosed, comprising a substrate (110), a unit cell (10) having a first transistor (11) and a second transistor (12), a gate layer (120) common to the first and second transistor, and a set of routing tracks (T1, T2, T3) for contacting the first and second transistor. Each one of the first and second transistors is formed of a stack of layers arranged between at least some of the routing tracks and the substrate, wherein each stack comprises a bottom terminal (130) arranged on the substrate, a channel (140) arranged on the bottom terminal and a top terminal (150) arranged on the channel. The channel of the first transistor is an N-type channel and the channel of the second transistor is a P-type channel. Further, the routing tracks comprises a pair of power routing tracks (T1, T2) arranged on opposite sides of the unit cell and adapted to contact the top terminal of the first and second transistor, and a gate track (T3) arranged between the pair of routing tracks and adapted to contact the gate layer at a position beside the unit cell.

    STANDARD CELL FOR VERTICAL TRANSISTORS
    2.
    发明公开
    STANDARD CELL FOR VERTICAL TRANSISTORS 审中-公开

    公开(公告)号：EP3343614A2

    公开(公告)日：2018-07-04

    申请号：EP17210357.4

    申请日：2017-12-22

    申请人： IMEC vzw ,  Vrije Universiteit Brussel

    发明人： RYCKAERT, Julien ,  HUYHN BAO, Trong

    IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2027/11816 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

    摘要： A standard cell semiconductor device (1) is disclosed, comprising a substrate (110), a unit cell (10) having a first transistor (11) and a second transistor (12), a gate layer (120) common to the first and second transistor, and a set of routing tracks (T1, T2, T3) for contacting the first and second transistor. Each one of the first and second transistors is formed of a stack of layers arranged between at least some of the routing tracks and the substrate, wherein each stack comprises a bottom terminal (130) arranged on the substrate, a channel (140) arranged on the bottom terminal and a top terminal (150) arranged on the channel. The channel of the first transistor is an N-type channel and the channel of the second transistor is a P-type channel. Further, the routing tracks comprises a pair of power routing tracks (T1, T2) arranged on opposite sides of the unit cell and adapted to contact the top terminal of the first and second transistor, and a gate track (T3) arranged between the pair of routing tracks and adapted to contact the gate layer at a position beside the unit cell.

    TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS
    6.
    发明公开
    TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
    法制造密度泛函单元的排列

    公开(公告)号：EP3161854A1

    公开(公告)日：2017-05-03

    申请号：EP14896073.5

    申请日：2014-06-25

    申请人： Intel Corporation

    发明人： ELSAYED, Rany, T. ,  GOEL, Niti ,  BOU-GHAZALE, Silvio, E. ,  ASKSAMIT, Randy, J.

    IPC分类号： H01L21/027 ,  H01L21/768

    CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11807 ,  H01L29/16 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H03K19/00

    摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

    摘要翻译： 技术是圆盘游离缺失用于形成使用下一代光刻（NGL）的过程，：例如电子束直写（EBDW）和极紫外光刻（EUVL），以形成所述阵列中的单元的边界功能性细胞的压实的阵列。 细胞的压实的阵列可用于现场可编程门阵列（FPGA）与逻辑单元配置的结构，静态随机存取存储器（SRAM）与位单元，或其它存储器或具有基于细胞的结构逻辑器件配置结构。 的技术可以用来获得在10面积％至50％的降低，例如，对于功能单元的阵列，因为NGL工艺允许更高的精度和对小区边界更靠近切割，相比于传统的193nm光刻 ， 此外，使用NGL工艺，以形成用于细胞因此可以减少光刻引起的变化，否则也将存在与常规的193nm的光刻法的边界。