公开(公告)号：EP0244925B1

公开(公告)日：1994-11-02

申请号：EP87300869.2

申请日：1987-01-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Shankar, Kapil ,  Agrawal, Om

IPC分类号： G05B19/04

CPC分类号： G06F9/30061 ,  G05B19/045 ,  G05B2219/21115 ,  G06F9/30036

公开(公告)号：EP0238230A3

公开(公告)日：1989-03-15

申请号：EP87301800.6

申请日：1987-03-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Shankar, Kapil

IPC分类号： G05B19/04

CPC分类号： G05B19/045

摘要： Method and apparatus providing a programmable logic device which has a high level subroutine stack element and a random access memory suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly-executed program which is easy to comprehend, verify and document. Subroutines are readily implemented by the controller by virtue of its last-in, first-out stack and a state counter which allow the contents of the counter to be "pushed" onto the stack upon invocation of the subroutine and "popped" from the stack upon return from the subroutine. Provision of the random access memory allows the controller to store information supplied from an external device, such as a central processing unit. The operation of the controller can be readily modified according to the control information stored in the memory by use of a high level language RAMREAD construct. The random access memory also provides scratch pad capability for the controller so that information written to a memory location, under control of a programmable OR array, can be used as a separate, independent counting and timing channel, in an exemplary application. The stack and/or the random access memory are suitable for inclusion in a controller of either a programmable logic array (PLA-), programmable array logic (PAL-), or a programmable read-only-memory (PROM-) based design.

公开(公告)号：EP0513983A1

公开(公告)日：1992-11-19

申请号：EP92302773.4

申请日：1992-03-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Ilgenstein, Kerry A. ,  Landers, George ,  Moench, Jerry ,  Schmitz, Nicholas A.

IPC分类号： H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品术语阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语阵列引导到选定的逻辑宏单元，使得没有产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可路由因素。 第二系列PLD具有比第一系列PLD更大的引脚与逻辑比。

公开(公告)号：EP0238230A2

公开(公告)日：1987-09-23

申请号：EP87301800.6

申请日：1987-03-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Shankar, Kapil

IPC分类号： G05B19/04

CPC分类号： G05B19/045

摘要： Method and apparatus providing a programmable logic device which has a high level subroutine stack element and a random access memory suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly-executed program which is easy to comprehend, verify and document. Subroutines are readily implemented by the controller by virtue of its last-in, first-out stack and a state counter which allow the contents of the counter to be "pushed" onto the stack upon invocation of the subroutine and "popped" from the stack upon return from the subroutine. Provision of the random access memory allows the controller to store information supplied from an external device, such as a central processing unit. The operation of the controller can be readily modified according to the control information stored in the memory by use of a high level language RAMREAD construct. The random access memory also provides scratch pad capability for the controller so that information written to a memory location, under control of a programmable OR array, can be used as a separate, independent counting and timing channel, in an exemplary application. The stack and/or the random access memory are suitable for inclusion in a controller of either a programmable logic array (PLA-), programmable array logic (PAL-), or a programmable read-only-memory (PROM-) based design.

摘要翻译： 逻辑器件包括响应于施加到器件的外部端子的信号的可编程阵列，用于产生多个逻辑信号。 多个可编程输出单元各自接收存储的逻辑信号并在预定的输入/输出端口返回产生信号。 多个存储单元每个存储预定的逻辑信号并产生信号作为回报。 计数器存储可选地递增或递减的计数值，并产生指示该值的计数信号。 设备接收并对计数信号和逻辑信号进行计数，以将计数值存储在先进先出的堆栈中，以去除堆栈的最后内容。 计数器还接收堆栈产生的信号。

公开(公告)号：EP0177280A2

公开(公告)日：1986-04-09

申请号：EP85306858.3

申请日：1985-09-26

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Brcich, Joseph

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/1733 ,  H03K19/17716

摘要： The present invention provides an output logic means for controlling configuration of an output for an integrated circuit which provides a logic signal including a register means responsive to a clock signal for latching the logic signal to provide a registered signal. An output select means receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback means provides a feedback signal as data which is selected by a feedback select means responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable means, responsive to a clock enable signal, enables or disables the clock signal to clock the register means. Accordingly, the register means, the output select means, the feedback means, and the clock enable means are all dynamically controllable by respective control signals.

摘要翻译： 本发明提供了一种用于控制集成电路的输出配置的输出逻辑装置，该集成电路提供包括响应于时钟信号的寄存器装置的逻辑信号，用于锁存逻辑信号以提供注册信号。 输出选择装置接收逻辑信号和注册信号，并且响应输出选择信号选择逻辑信号或注册信号。 反馈装置提供作为数据的反馈信号，该数据由反馈选择装置选择，响应于用于选择逻辑信号或注册信号的反馈选择信号作为反馈信号。 此外，响应于时钟使能信号的时钟信号使能装置启用或禁用时钟信号来对寄存器装置进行时钟。 因此，寄存器装置，输出选择装置，反馈装置和时钟使能装置都可以由相应的控制信号动态地控制。

公开(公告)号：EP0238230B1

公开(公告)日：1992-12-23

申请号：EP87301800.6

申请日：1987-03-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Shankar, Kapil

IPC分类号： G05B19/04

CPC分类号： G05B19/045

公开(公告)号：EP0177280B1

公开(公告)日：1991-05-29

申请号：EP85306858.3

申请日：1985-09-26

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Brcich, Joseph

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/1733 ,  H03K19/17716

公开(公告)号：EP0244925A3

公开(公告)日：1990-03-28

申请号：EP87300869.2

申请日：1987-01-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Shankar, Kapil ,  Agrawal, Om

IPC分类号： G05B19/04

CPC分类号： G06F9/30061 ,  G05B19/045 ,  G05B2219/21115 ,  G06F9/30036

摘要： Method and apparatus providing a programmable logic device which has a high level counter element and a programmable AND array suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly- executed program which is easy to comprehend, verify and document. Moore and Mealy state machines are readily implemented by the controller by virtue of its programmable AND array and counter which allow the next-state and output to be based on the contents of the counter as well as any set of input signals. Conditional testing can be made entirely state dependent, partially-state dependent, or state-independent. Multiway branching is also readily implemented since the presence of the programmable AND array allows the user to specify a number of sets of input conditions, so that from a given state, as determined by the counter contents, each set of input condition gives rise to a transition to a specified next state. Instruction decoding for the controller is preformed in the programmable AND array, and thus can be specified by the designer in the high-level software method of the invention. Accordingly, instructions can be stored in the AND array in a logical form directly usable by the hardware. The counter is preferably of the Gray-code type so as to minimize instabilities in the output signals and to permit easy optimization of Boolean expressions involving the state of the device. Dedicated buried registers are provided as are dedicated feedback paths from the output registers, dedicated registers and counter to the AND array. Two separate OR arrays are provided, one generating output signals, the other generating control sequencing signals.

公开(公告)号：EP0177280A3

公开(公告)日：1988-01-07

申请号：EP85306858

申请日：1985-09-26

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, Om ,  Brcich, Joseph

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/1733 ,  H03K19/17716

摘要： The present invention provides an output logic means for controlling configuration of an output for an integrated circuit which provides a logic signal including a register means responsive to a clock signal for latching the logic signal to provide a registered signal. An output select means receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback means provides a feedback signal as data which is selected by a feedback select means responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable means, responsive to a clock enable signal, enables or disables the clock signal to clock the register means. Accordingly, the register means, the output select means, the feedback means, and the clock enable means are all dynamically controllable by respective control signals.

公开(公告)号：EP0244925A2

公开(公告)日：1987-11-11

申请号：EP87300869.2

申请日：1987-01-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Shankar, Kapil ,  Agrawal, Om

IPC分类号： G05B19/04

CPC分类号： G06F9/30061 ,  G05B19/045 ,  G05B2219/21115 ,  G06F9/30036

摘要： Method and apparatus providing a programmable logic device which has a high level counter element and a programmable AND array suitable for control applications. The method utilizes high level constructs bearing a one-to-one relationship to the architecture of the apparatus so that the design of the controller is facilitated resulting in a rapidly- executed program which is easy to comprehend, verify and document. Moore and Mealy state machines are readily implemented by the controller by virtue of its programmable AND array and counter which allow the next-state and output to be based on the contents of the counter as well as any set of input signals. Conditional testing can be made entirely state dependent, partially-state dependent, or state-independent. Multiway branching is also readily implemented since the presence of the programmable AND array allows the user to specify a number of sets of input conditions, so that from a given state, as determined by the counter contents, each set of input condition gives rise to a transition to a specified next state. Instruction decoding for the controller is preformed in the programmable AND array, and thus can be specified by the designer in the high-level software method of the invention. Accordingly, instructions can be stored in the AND array in a logical form directly usable by the hardware. The counter is preferably of the Gray-code type so as to minimize instabilities in the output signals and to permit easy optimization of Boolean expressions involving the state of the device. Dedicated buried registers are provided as are dedicated feedback paths from the output registers, dedicated registers and counter to the AND array. Two separate OR arrays are provided, one generating output signals, the other generating control sequencing signals.

摘要翻译： 提供可编程逻辑器件的方法和装置，其具有适用于控制应用的高级计数器元件和可编程AND阵列。 该方法利用与设备的架构具有一对一关系的高级结构，使得控制器的设计变得容易，导致易于理解，验证和记录的快速执行的程序。 Moore和Mealy状态机通过其可编程的AND阵列和计数器由控制器容易地实现，其允许下一状态和输出基于计数器的内容以及任何输入信号集合。 条件测试可以完全取决于状态，部分依赖于状态或状态无关多路分支也容易实现，因为可编程AND阵列的存在允许用户指定多组输入条件，从而从给定的 状态，由计数器内容确定，每组输入条件导致转换到指定的下一状态。 用于控制器的指令解码在可编程AND阵列中执行，因此可以由本发明的高级软件方法中的设计者指定。 因此，指令可以以硬件直接使用的逻辑形式存储在AND阵列中。 该计数器最好是格雷码型，以便最小化输出信号的不稳定性，并允许容易地优化涉及器件状态的布尔表达式。 专用的寄存器是从输出寄存器，专用寄存器和与数组的计数器的专用反馈路径。 提供两个单独的OR阵列，一个产生输出信号，另一个产生控制定序信号。