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公开(公告)号：EP1307818A2
公开(公告)日：2003-05-07
申请号：EP01959298.9
申请日：2001-07-27
IPC分类号： G06F13/00
CPC分类号： G06F9/52
摘要： A distributed memory multiprocessing computer system includes two or more processing nodes (22A-D) interconnected by point-to-point communication links (34). A lock acquisition request (40) from a lock requesting node (22) is placed into service by an arbitrating node (22) when no previous lock requests (40) are pending for service. The arbitrating node (22) broadcasts a message (82) to all nodes (22A-D), which, in turn, respond with a corresponding message (84) to inform the arbitrating node (22) of cessation of issuance of new requests (40). The arbitrating node (22) then informs the lock requesting node (22) of the requesting node's lock ownership. After completion of lock operations, the lock requesting node (22) sends a lock release request (40) to the arbitrating node (22), which, in turn, informs all processing nodes (22A-D) of lock release by broadcasting another message (82) within the system. The messaging protocol is completed when each node (22A-D) responds to the arbitrating node (22), which, in turn, sends a final target done message (85) to the lock requesting node (22).
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2.发明公开FLEXIBLE PROBE/PROBE RESPONSE ROUTING FOR MAINTAINING COHERENCY 有权灵活的探测命令/ SONDIERUNGRESPONS路由维护内存一致性
公开(公告)号：EP1141839A1
公开(公告)日：2001-10-10
申请号：EP99946646.9
申请日：1999-08-26
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0817
摘要： A computer system (10) may include multiple processing nodes (12A-12D), one or more of which may be coupled to separate memories (14A-14D) which may form a distributed memory system. The processing nodes (12A-12D) may include caches (90, 94), and the computer system (10) may maintain coherency between the caches (90, 94) and the distributed memory system. Particularly, the computer system (10) may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node (12A; 12B; 12C; 12D) to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included.
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公开(公告)号：EP1244962B1
公开(公告)日：2003-10-08
申请号：EP00964913.8
申请日：2000-08-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular instruction operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations which are to be executed non-speculatively may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.
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5.发明公开SYSTEM AND METHOD FOR SEPARATE VIRTUAL CHANNELS FOR POSTED REQUESTS IN A MULTIPROCESSOR SYSTEM 有权系统和方法一种用于在MULITPROZESSORSYSTEM停产要求独立的虚拟通道
公开(公告)号：EP1314094A2
公开(公告)日：2003-05-28
申请号：EP01959284.9
申请日：2001-07-27
CPC分类号： G06F13/14 , G06F13/4265
摘要： A computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted requests through coherent and noncoherent fabrics within the computer system. The computer system also allocate separate resources to each of the virtual channels, thus allowing posted requests to become unordered with other requests from the same source. Such an implementation allows the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e.g., the Peripheral Component Interconnect Bus).
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公开(公告)号：EP1244961B1
公开(公告)日：2004-03-17
申请号：EP00951015.7
申请日：2000-08-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3826 , G06F9/3838
摘要： A processor (10) employs a store to load forward (STLF) predictor (60) which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor (60) is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor (60) may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor (60) as dependent upon a particular store and the dependency does not actually occur.
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公开(公告)号：EP1244962A1
公开(公告)日：2002-10-02
申请号：EP00964913.8
申请日：2000-08-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular instruction operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations which are to be executed non-speculatively may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.
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8.发明授权CACHE WHICH PROVIDES PARTIAL TAGS FROM NON-PREDICTED WAYS TO DIRECT SEARCH IF WAY PREDICTION MISSES 有权缓存提供部分标签与非上述内容为WEGVORHERSAGEFEHLGRIFFEN导出搜索
公开(公告)号：EP1244970B1
公开(公告)日：2003-06-04
申请号：EP00951019.9
申请日：2000-08-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F9/30149 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F2212/6082 , Y02D10/13
摘要： A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.
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9.发明公开CACHE WHICH PROVIDES PARTIAL TAGS FROM NON-PREDICTED WAYS TO DIRECT SEARCH IF WAY PREDICTION MISSES 有权CACHE用于提供DUE TO WEGVORHERSAGEFEHLGRIFFEN NON-前述规定局部标签的直接搜索
公开(公告)号：EP1244970A1
公开(公告)日：2002-10-02
申请号：EP00951019.9
申请日：2000-08-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F9/30149 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F2212/6082 , Y02D10/13
摘要： A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.
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公开(公告)号：EP1244961A1
公开(公告)日：2002-10-02
申请号：EP00951015.7
申请日：2000-08-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3826 , G06F9/3838
摘要： A processor (10) employs a store to load forward (STLF) predictor (60) which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor (60) is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor (60) may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor (60) as dependent upon a particular store and the dependency does not actually occur.
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