公开(公告)号：EP1034619B1

公开(公告)日：2008-11-26

申请号：EP98958071.7

申请日：1998-11-20

申请人： ATMEL CORPORATION

发明人： PATHAK, Jagdish ,  PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E. ,  HANGZO, Nianglamching

IPC分类号： H03K17/22

CPC分类号： H03K17/223

摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

公开(公告)号：EP1086449A1

公开(公告)日：2001-03-28

申请号：EP99925798.3

申请日：1999-05-25

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  ROSENDALE, Glen, A. ,  HANGZO, Nianglamching

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/2074 ,  G09G3/3677 ,  G09G2300/0876 ,  G09G2310/0289

摘要： A circuit (202; 204) for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor (308; 308') powered by a high voltage power source to bias a pass transistor (114; 124) at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor (304; 304') provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor (306; 306') operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.

公开(公告)号：EP1034619A1

公开(公告)日：2000-09-13

申请号：EP98958071.7

申请日：1998-11-20

申请人： ATMEL CORPORATION

发明人： PATHAK, Jagdish ,  PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E. ,  HANGZO, Nianglamching

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

公开(公告)号：EP1301982B1

公开(公告)日：2006-08-02

申请号：EP01928713.5

申请日：2001-04-20

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  KUO, Harry, H.

IPC分类号： H02M1/00

CPC分类号： G05F1/465

摘要： A voltage regulator circuit (11) that receives an input signal (450) and provides an output signal (600) that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit (500) in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. In the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit (500) clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit (500) is disabled and one of a plurality of voltage maintaining subcircuits (550, 560, 570) takes control so that the output voltage remains at the desired voltage for the internal circuit.

公开(公告)号：EP1234299A1

公开(公告)日：2002-08-28

申请号：EP00963636.6

申请日：2000-09-19

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E.

IPC分类号： G09G3/36

CPC分类号： G09G3/3659 ,  G09G2300/0814 ,  G09G2300/0842 ,  G09G2300/0852

摘要： A driver circuit for use in an array (41) of picture elements (43) in a liquid crystal display is capable of displaying one set of image data while receiving a second set of image data. A first select switch transistor (S1) responsive to a first select signal (R 1,A) controls the coupling of a first image to a first storage capacitor (C1). A second select switch transistor (S2) responsive to a second select signal (R 1,B) controls the coupling of a second image to a second storage capacitor (C2). The first storage capacitor (C1) may be selectively coupled to an output node (PXL) by means of a first enable switch transistor (E1) responsive to a first enable signal (EN 1,1). The second storage capacitor (C2) may be selectively coupled to the same output node (PXL) by means of a second enable switch transistor (E2) responsive to a second enable signal (EN 2,1). By proper manipulation of the switch transistors, one storage capacitor may be coupled to the output node while the other storage capacitor is isolated from the output node and receiving new image data.

公开(公告)号：EP0660963B1

公开(公告)日：1998-05-20

申请号：EP93921522.4

申请日：1993-09-13

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E.

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/067 ,  G11C7/1006 ,  G11C16/26

摘要： A read circuit for a semiconductor memory that includes a pass transistor (47) between the output (29) of a first sense amplifier (19) reading the memory and a latch (49). The pass transistor blocks transmission of the sense amplifier's output to the latch whenever a noise glitch producing condition is sensed. A second sense amplifier (39) connected through the same conductive line (21) to the memory cell array as the first sense amplifier has a faster response and lower current threshold in order to detect the glitch producing condition. A pulse generator (43) receives the output (41) of the second sense amplifier and provides a control signal pulse of predetermined duration following detection of the glitch producing condition by the second sense amplifier. The pulse is received by a control gate (48) of the pass transistor, turning the transistor off during the duration of the pulse.

公开(公告)号：EP0757835A1

公开(公告)日：1997-02-12

申请号：EP95917760.0

申请日：1995-04-28

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E.

IPC分类号： H01L21 ,  G11C16 ,  H01L27 ,  H01L29

CPC分类号： G11C16/0433 ,  H01L27/115

摘要： A non-volatile programmable circuit having programming bitlines (PBL; 36) and read bitlines (RBL; 37), a non-volatile memory cell (30), and a read select transistor (34), and a method for its operation. The non-volatile memory cell is programmable through the progamming bitline. The read select transistor is connected between the non-volatile memory cell and the read bitline. During read operation, the programming bitline is grounded and programmed information is readable onto the read bitline. During programming operation, the read bitline is grounded, and programmed information is programmable into the non-volatile memory cell for storage and retention.

公开(公告)号：EP1123556B1

公开(公告)日：2006-01-25

申请号：EP99930292.0

申请日：1999-06-15

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E.

IPC分类号： H01H37/76 ,  G11C17/16 ,  G11C29/00

CPC分类号： G11C17/18

摘要： A fuse circuit (100) includes a fusible element (110) and a feedback path which causes the circuit to behave as if the fusible element (110) is fully blown even though the fusible element (110) in fact is partially intact. While a partially intact fuse normally would result in a continuous drain of power, the feedback path cuts of the current flow through the partially intact fusible element (110).

公开(公告)号：EP0954864B1

公开(公告)日：2003-05-14

申请号：EP98960402.0

申请日：1998-11-19

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E. ,  HANGZO, Nianglamching

IPC分类号： G11C8/00

CPC分类号： G11C7/1039

摘要： A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

公开(公告)号：EP1301982A2

公开(公告)日：2003-04-16

申请号：EP01928713.5

申请日：2001-04-20

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  KUO, Harry, H.

IPC分类号： H02M1/00

CPC分类号： G05F1/465

摘要： A voltage regulator circuit (11) that receives an input signal (450) and provides an output signal (600) that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit (500) in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. In the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit (500) clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit (500) is disabled and one of a plurality of voltage maintaining subcircuits (550, 560, 570) takes control so that the output voltage remains at the desired voltage for the internal circuit.