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公开(公告)号：EP0954864B1
公开(公告)日：2003-05-14
申请号：EP98960402.0
申请日：1998-11-19
申请人： ATMEL CORPORATION
IPC分类号： G11C8/00
CPC分类号： G11C7/1039
摘要： A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
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公开(公告)号：EP1034619B1
公开(公告)日：2008-11-26
申请号：EP98958071.7
申请日：1998-11-20
申请人： ATMEL CORPORATION
发明人： PATHAK, Jagdish , PATHAK, Saroj , ROSENDALE, Glen, A. , PAYNE, James, E. , HANGZO, Nianglamching
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).
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3.发明公开
公开(公告)号：EP1086449A1
公开(公告)日：2001-03-28
申请号：EP99925798.3
申请日：1999-05-25
申请人： ATMEL CORPORATION
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/2074 , G09G3/3677 , G09G2300/0876 , G09G2310/0289
摘要： A circuit (202; 204) for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor (308; 308') powered by a high voltage power source to bias a pass transistor (114; 124) at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor (304; 304') provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor (306; 306') operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
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公开(公告)号：EP1034619A1
公开(公告)日：2000-09-13
申请号：EP98958071.7
申请日：1998-11-20
申请人： ATMEL CORPORATION
发明人： PATHAK, Jagdish , PATHAK, Saroj , ROSENDALE, Glen, A. , PAYNE, James, E. , HANGZO, Nianglamching
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).
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公开(公告)号：EP1192475A2
公开(公告)日：2002-04-03
申请号：EP00936229.4
申请日：2000-05-23
申请人： ATMEL CORPORATION
IPC分类号： G01R31/28
CPC分类号： G11C29/02 , G01R31/31855
摘要： A video chip (100) includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register (122, 124). There is a circuit for the column lines (114) and for the row lines (112). A bit pattern is driven onto the column (114) or the row lines (112) and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
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公开(公告)号：EP1078370A1
公开(公告)日：2001-02-28
申请号：EP99914242.5
申请日：1999-03-29
申请人： ATMEL CORPORATION
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/065 , G11C7/1036
摘要： A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.
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公开(公告)号：EP0954864A1
公开(公告)日：1999-11-10
申请号：EP98960402.0
申请日：1998-11-19
申请人： ATMEL CORPORATION
CPC分类号： G11C7/1039
摘要： A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
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