公开(公告)号：EP3255635A1

公开(公告)日：2017-12-13

申请号：EP17169670.1

申请日：2017-05-05

申请人： Altera Corporation

发明人： Chu, Pohrong Rita

IPC分类号： G11C7/10 ,  G11C8/16

CPC分类号： G11C8/12 ,  G06F5/00 ,  G06F9/30141 ,  G11C7/1075 ,  G11C8/00 ,  G11C8/16

摘要： Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

摘要翻译： 集成电路可以包括存储器元件电路。 存储器元件电路可以包括多个双端口存储器元件，其被控制以有效地形成具有多个读取和写入端口的多端口存储器元件。 相应的双端口存储器元件组可以耦合到每个写入端口。 写入数据可以同时通过一个或多个写入端口接收并存储在存储体上。 开关电路可以耦合在存储体元件电路的读取端口和存储体之间。 可以使用由基于逻辑XOR的控制电路生成的读取控制信号来控制开关电路。 控制电路可以包括存储与写入数据相关联的寻址信号的双端口存储器元件。 读取控制信号可以控制开关电路在数据读取操作期间选择性地将最近写入的数据路由到对应的读取端口。