公开(公告)号：EP1907944A2

公开(公告)日：2008-04-09

申请号：EP06787441.2

申请日：2006-07-18

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yosef ,  YUKNA, Gregory, M.

IPC分类号： G06F17/10

CPC分类号： H03H17/0263 ,  G06F7/22 ,  G06F7/544

摘要： An instruction based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; and applies at least one instruction for enabling indication of at least one of the maximum, minimum, median filter values.

公开(公告)号：EP1941370A2

公开(公告)日：2008-07-09

申请号：EP06817002.6

申请日：2006-10-17

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua A. ,  STEIN, Yosef ,  MAYER, Christopher M.

IPC分类号： G06F12/00

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/345 ,  G06F9/3552 ,  G09C1/00 ,  H04L9/06 ,  H04L2209/122

摘要： Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.

公开(公告)号：EP1825354A2

公开(公告)日：2007-08-29

申请号：EP05849642.3

申请日：2005-11-21

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  STEIN, Yosef ,  KABLOTSKY, Joshua

IPC分类号： G06F7/00

CPC分类号： G06F7/724 ,  H03M13/1515 ,  H03M13/158

摘要： A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

公开(公告)号：EP2130132A1

公开(公告)日：2009-12-09

申请号：EP08726448.7

申请日：2008-03-05

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua ,  STEIN, Yosef

IPC分类号： G06F15/00

CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30018 ,  G06F9/3824 ,  G06F2205/126

摘要： A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

公开(公告)号：EP1999607A2

公开(公告)日：2008-12-10

申请号：EP07752132.6

申请日：2007-03-01

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yossef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M. ,  HAYDEN, John, A.

IPC分类号： G06F15/00

CPC分类号： G06F9/30109 ,  G06F7/57 ,  G06F7/766 ,  G06F7/768 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3013

摘要： Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.

公开(公告)号：EP2130132B1

公开(公告)日：2013-05-29

申请号：EP08726448.7

申请日：2008-03-05

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua ,  STEIN, Yosef

IPC分类号： G06F15/00 ,  G06F5/10

CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30018 ,  G06F9/3824 ,  G06F2205/126

公开(公告)号：EP1941378A2

公开(公告)日：2008-07-09

申请号：EP06817042.2

申请日：2006-10-17

申请人： Analog Devices, Inc.

发明人： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yosef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

IPC分类号： G06F15/00

CPC分类号： G06F9/3001 ,  G06F9/345 ,  G06F9/3885

摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.