公开(公告)号：EP2930849B1

公开(公告)日：2019-05-01

申请号：EP15159281.3

申请日：2015-03-16

Applicant: Analog Devices Global Unlimited Company

Inventor： Zhao, Jialin ,  Schreier, Richard E. ,  Silva, Jose Barreiro ,  Shibata, Hajime ,  Yang, Wenhua W. ,  Dong, Yunzhi

IPC: H03M1/10 ,  H03M3/04 ,  H03M1/74

公开(公告)号：EP3182599A1

公开(公告)日：2017-06-21

申请号：EP16203106.6

申请日：2016-12-09

Applicant: Analog Devices Global

Inventor： Meng, Qingdong ,  Shibata, Hajime ,  Schreier, Richard E. ,  McCormick, Martin Steven ,  Dong, Yunzhi ,  Silva, Jose Barreiro ,  Zhao, Jialin ,  Paterson, Donald W. ,  Yang, Wenhua W.

IPC: H03M3/00

CPC classification number: H03M1/08 ,  H03M1/124 ,  H03M3/344 ,  H03M3/414

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

Abstract translation: 对于连续时间多级噪声整形模数转换器（CT MASH ADC），量化噪声消除通常需要对传输函数进行精确估计，例如，前端调制​​器的噪声传递函数以及前端调制器的信号传递函数 后端调制器。 为了提供量化噪声消除，数字量化噪声消除滤波器自适应跟踪由于积分器增益误差，闪存至DAC时序误差以及级间增益和时序误差而导致的传递函数变化。 通过注入的最大长度线性反馈移位寄存器（LFSR）序列和调制器输出之间的直接互相关执行跟踪传递函数，然后通过用可编程有限脉冲响应（PFIR）对传递函数进行精确建模来校正这些非理想效应， 过滤器。

公开(公告)号：EP2913929A2

公开(公告)日：2015-09-02

申请号：EP15156825.0

申请日：2015-02-26

Applicant: Analog Devices Global

Inventor： Dong, Yunzhi ,  Li, Zhao ,  Schreier, Richard E. ,  Shibata, Hajime ,  Caldwell, Trevor Clifford

IPC: H03M1/14

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格的延迟元件来实现高性能CT流水线ADC和CT delta-sigma（“£”）ADC。 使用基于LC晶格的延迟元件为具有良好控制阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路部分，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

公开(公告)号：EP2913929A3

公开(公告)日：2016-03-02

申请号：EP15156825.0

申请日：2015-02-26

Applicant: Analog Devices Global

Inventor： Dong, Yunzhi ,  Li, Zhao ,  Schreier, Richard E. ,  Shibata, Hajime ,  Caldwell, Trevor Clifford

IPC: H03M1/14 ,  H03K5/159 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

公开(公告)号：EP2863547A3

公开(公告)日：2015-06-17

申请号：EP14188331.4

申请日：2014-10-09

Applicant: Analog Devices Global

Inventor： Dong, Yunzhi ,  Shibata, Hajime ,  Yang, Wenhua ,  Schreier, Richard

IPC: H03M3/04

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analogto-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (Δ∑) modulator is provided at the front-end of the MASH ADC, and another full Δ∑ modulator is provided at the back-end of the MASH ADC. The front-end Δ∑ modulator digitizes an analog input signal, and the back-end Δ∑ modulator digitizes an error between the output of the front-end Δ∑ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

公开(公告)号：EP2930849A1

公开(公告)日：2015-10-14

申请号：EP15159281.3

申请日：2015-03-16

Applicant: Analog Devices Global

Inventor： Zhao, Jialin ,  Schreier, Richard E. ,  Silva, Jose Barreiro ,  Shibata, Hajime ,  Yang, Wenhua W. ,  Dong, Yunzhi

IPC: H03M1/10 ,  H03M3/04 ,  H03M1/74

CPC classification number: H03M3/378 ,  H03M1/1019 ,  H03M1/1038 ,  H03M1/74 ,  H03M3/37 ,  H03M3/384 ,  H03M3/388 ,  H03M3/464

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不是理想的，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。

公开(公告)号：EP2863547A2

公开(公告)日：2015-04-22

申请号：EP14188331.4

申请日：2014-10-09

Applicant: Analog Devices Global

Inventor： Dong, Yunzhi ,  Shibata, Hajime ,  Yang, Wenhua ,  Schreier, Richard

IPC: H03M3/04

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analogto-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (Δ∑) modulator is provided at the front-end of the MASH ADC, and another full Δ∑ modulator is provided at the back-end of the MASH ADC. The front-end Δ∑ modulator digitizes an analog input signal, and the back-end Δ∑ modulator digitizes an error between the output of the front-end Δ∑ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract translation: 本公开描述了用于将模拟输入信号转换成数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别是，在MASH ADC的前端提供了一个完整的Δ-Σ调制器，而在MASH ADC的后端提供了另一个完整的ΔΣ调制器。 前端ΔΣ调制器将模拟输入信号数字化，后端ΔΣ调制器将前端ΔΣ调制器的输出与（原始）模拟输入信号之间的误差数字化。 在后端调制器将（全）前端调制器的误差数字化的这种配置中，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂性（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。