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1.发明公开
公开(公告)号：EP2560285A3
公开(公告)日：2017-01-18
申请号：EP12175266.1
申请日：2012-07-06
发明人： Braswell, Brandt
摘要： An analog-to-digital converter (ADC) (10) includes a continuous time filter (14), a quantizer (18), a continuous time digital-to-analog converter (20), a discrete time DAC (24), and a switch (26). The quantizer (18) has an input terminal coupled to the output terminal of the continuous time filter (14), and a plurality of output terminals. The continuous time DAC (20) has a plurality of input terminals coupled to the plurality of output terminals of the quantizer (18), and an output terminal. The discrete time DAC (24) has a plurality of input terminals coupled to the plurality of output terminals of the quantizer (18), and an output terminal. The switch (26) has a first input terminal coupled to the output terminal of the continuous time DAC (20), a second input terminal coupled to the output terminal of the discrete time DAC (24), and an output terminal coupled to the input terminal of the continuous time filter (14).
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2.发明公开PROCEDE DE CONTROLE DU RETARD DE BOUCLE DANS UN MODULATEUR SIGMA-DELTA ET MODULATEUR METTANT EN UVRE LE PROCEDE 审中-公开FOR环路延迟控制方法的Σ-Δ调制器和sigma-delta调制器采用这种方法
公开(公告)号：EP2342829A1
公开(公告)日：2011-07-13
申请号：EP09756277.1
申请日：2009-10-29
申请人： THALES
发明人： HODE, Jean-Michel
摘要： The invention relates to a method for controlling the loop delay in a sigma-delta modulator that consists of a loop comprising at least one integrator (400, 500), an analog-to-digital converter ADC (401, 501), a digital-to-analog converter DAC (402, 502) and an adder-subtractor (403, 503), characterised in that at least one phase control programmable digital control (φ
1 , φ
2 ) representing an offset is applied to one of the clock signals of the loop converters in order to adjust the relative phase between the clock signal h
1 (t) of the ADC converter (401, 501) and the clock signal h
2 (t) of the DAC converter (402, 502). The invention also relates to a sigma-delta modulator for implementing said method.-
3.发明公开PROCEDE DE CORRECTION DES DECENTRAGES EN AMPLITUDE ET EN PHASE D'UN MODULATEUR SIGMA-DELTA ET MODULATEUR METTANT EN UVRE LE PROCEDE 审中-公开纠正和振幅相位偏移的Σ-Δ调制器和sigma-delta调制器采用这种方法
公开(公告)号：EP2342826A1
公开(公告)日：2011-07-13
申请号：EP09753063.8
申请日：2009-10-29
申请人： THALES
发明人： HODE, Jean-Michel
摘要： The invention relates to a method for correcting amplitude and phase offsets in a sigma-delta modulator that includes a loop comprising at least one integrator (200, 300) consisting of a filter (201, 301) and an amplifier (202, 302), an analog-to-digital converter ADC (203, 303), a digital-to-analog converter DAC (204, 304) and an adder-subtractor (205, 305). The open-loop amplitude/phase frequency response ( ρ
n , φ
n ) of the modulator is digitally estimated. A phase offset value (Δφ) and an amplitude offset value (Δp) are calculated by comparing the estimated open-loop amplitude/phase frequency response ( ρ
n , φ
n ) with a reference amplitude/phase frequency response ( ρ
n
(ref) , φ
n
(ref ) ). The phase and gain offsets of the loop are compensated for on the basis of the estimated offset values (Δp, Δφ). The invention also relates to a sigma-delta modulator implementing said method.-
公开(公告)号：EP1713175B1
公开(公告)日：2007-10-24
申请号：EP06007862.3
申请日：2006-04-13
发明人： Kishida, Masahiro
IPC分类号： H03F3/217
CPC分类号： H03F3/217 , H03F2200/03 , H03F2200/331 , H03M3/37 , H03M3/502
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5.发明授权A frequency translating coherent analog to digital conversion system for modulated signals 失效频率转换为调制信号相干A / D转换系统
公开(公告)号：EP0525969B1
公开(公告)日：1997-09-03
申请号：EP92305711.1
申请日：1992-06-22
申请人： MOTOROLA INC.
IPC分类号： H03M3/02
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6.发明公开Sigma-delta analog-to-digital converter (ADC) with feedback compensation and method therefor 失效Sigma-Delta Analog-Digitalwandler（ADC）mitRückkopplungskompensationundzugehörigesVerfahren。
公开(公告)号：EP0658008A2
公开(公告)日：1995-06-14
申请号：EP94118912.8
申请日：1994-12-01
申请人： MOTOROLA, INC.
发明人： Seaberg, Eric C.
IPC分类号： H03M3/02
摘要： A sigma-delta analog-to-digital converter (ADC) (80) includes first (81) and second (82) integrators, a quantizer (83) connected to an output of the second integrator (82), and a feedback circuit (84) connected to the output of the quantizer (83). In order to avoid the effects of delays through actual circuit elements, the feedback circuit (84) keeps the feedback signal to the first integrator (81) in a high-impedance state until the quantizer (83) resolves the output of the second integrator (82). Thus, the first integrator (81) avoids temporarily summing a possibly incorrect feedback signal. In addition, the feedback circuit (84) also keeps the first integrator (81) from integrating a sum of an input signal and the feedback signal until the feedback signal is driven to its correct state in response to the output of the quantizer (83). To accomplish these results, the feedback circuit (84) includes a compensation circuit (151) for continually determining when the quantizer (83) resolves.
摘要翻译： Σ-Δ模数转换器（80）包括第一（81）和第二（82）积分器，连接到第二积分器（82）的输出的量化器（83）和反馈电路 84）连接到量化器（83）的输出。 为了避免通过实际电路元件的延迟的影响，反馈电路（84）将反馈信号保持在第一积分器（81）处于高阻抗状态，直到量化器（83）解决第二积分器的输出（ 82）。 因此，第一积分器（81）避免对可能不正确的反馈信号进行临时求和。 此外，反馈电路（84）还保持第一积分器（81）不对输入信号和反馈信号的和进行积分，直到响应于量化器（83）的输出将反馈信号驱动到其正确状态， 。 为了实现这些结果，反馈电路（84）包括用于连续地确定量化器（83）何时解析的补偿电路（151）。
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7.发明公开A frequency translating coherent analog to digital conversion system for modulated signals 失效频率转换相关模拟转换为数字转换系统的调制信号
公开(公告)号：EP0525969A3
公开(公告)日：1993-08-25
申请号：EP92305711.1
申请日：1992-06-22
申请人： MOTOROLA INC.
IPC分类号： H03M3/02
摘要： An analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), an A/D converter (18), an oscillator (12), and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.
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公开(公告)号：EP3353896A1
公开(公告)日：2018-08-01
申请号：EP16766119.8
申请日：2016-08-24
发明人： RAJAEE, Omid , HAN, Changsok , DAI, Liang , MIRHAJ, Seyed Arash , KIRAN, Ganesh
摘要： Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.
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公开(公告)号：EP3340474A1
公开(公告)日：2018-06-27
申请号：EP16205911.7
申请日：2016-12-21
申请人： Intel IP Corporation
摘要： Analog-to-digital converter devices and methods are provided, where feedback using a nonlinear digital-to-analog converter is used. In some implementations, such a nonlinear digital-to-analog converter feedback may be used to compensate extra loop delay while maintaining stability and/or not injecting any additional noise.
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公开(公告)号：EP3158646A1
公开(公告)日：2017-04-26
申请号：EP15809124.9
申请日：2015-06-19
IPC分类号： H03M3/02
摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.
摘要翻译： 一种增加动态范围的Δ-Σ调制器。 ΔΣ调制器具有多个ADC和多个DAC，多个ADC和DAC连接成一个环路。 多个ADC与输入的模拟信号耦合。 时钟发生器提供控制多个ADC和多个DAC的多个时钟信号，时钟信号在时域中彼此相对偏移，从而使得多个ADC中的每个ADC一次一个，并且每个DAC 在多个DAC中一次一个，使得ΔΣ调制器以交错方式处理输入模拟信号中的数据。 Δ-Σ调制器在环路的正向路径中具有N阶滤波器。
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