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公开(公告)号：EP0320748A2
公开(公告)日：1989-06-21
申请号：EP88120320.2
申请日：1988-12-06
发明人： Vitiello, Paolo , Bergamo, Luca
IPC分类号： H03L7/14
CPC分类号： H03L1/00 , H03L7/10 , H03L2207/06
摘要： Self adjusting phase lock circuit in which a frequency and/or phase comparator (1) compares the frequency and/or phase of a reference signal FVCO with the frequency and/or phase of a frequency or phase modulated signal RD to generate an error signal input to an integrating network (3,4), which in turn generates an error voltage related to the frequency/phase error of the two signals, said voltage being input to the control input of a voltage controlled oscillator (2) which generates reference signal FVCO as a function of the error voltage and of an adjusting voltage received at an adjusting input, wherein self adjusting means are provided consisting in a fixed reference voltage periodically input to the oscillator control input as a substitute for the error voltage, in a source of a fixed frequency signal, periodically input to the comparator (9) as a substitute for the modulated signal, in an operational network generating from the error voltage a feedback signal (VRANGE) periodically input to the adjusting input of the oscillator (2) and hold at said input by sample and hold circuits (10,11,17), so that the adjusting voltage VRANGE is periodically adjusted in automatic way to provide to the phase lock circuit an operative condition permanently close to a nominal working point, independently of thermal drift and performance spread of the used components.
摘要翻译： 自调节锁相电路，其中频率和/或相位比较器（1）将参考信号FVCO的频率和/或相位与频率或相位调制信号RD的频率和/或相位进行比较，以产生误差信号输入 到积分网络（3,4），其进而产生与两个信号的频率/相位误差相关的误差电压，所述电压被输入到压控振荡器（2）的控制输入端，该压控振荡器产生参考信号FVCO 作为在调整输入处接收的误差电压和调整电压的函数，其中提供自调节装置，其中包括以周期性地输入到振荡器控制输入的固定参考电压作为误差电压的替代， 在由误差电压生成的运行网络中周期性地输入到比较器（9）作为调制信号的替代，固定频率信号周期性地将反馈信号（VRANGE） 输入到振荡器（2）的调整输入端，并通过采样和保持电路（10,11,17）保持在所述输入端，使得调节电压VRANGE以自动方式周期性地调整，以向锁相电路提供一个操作 条件永久地接近标称工作点，独立于所使用部件的热漂移和性能扩散。
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公开(公告)号：EP0274591B1
公开(公告)日：1992-04-15
申请号：EP87116273.1
申请日：1987-11-05
发明人： Vitiello, Paolo
CPC分类号： H03L7/089 , G11B20/1403
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公开(公告)号：EP0274591A1
公开(公告)日：1988-07-20
申请号：EP87116273.1
申请日：1987-11-05
发明人： Vitiello, Paolo
CPC分类号： H03L7/089 , G11B20/1403
摘要： Phase lock circuit for generating a periodical reference signal having a variable frequency, locked to the frequency of a sequence of electrical pulses corresponding to information (RD) read out from a movable magnetic media where information is recorded in phase modulation as to a nominal frequency, comprising a phase comparator (1) for generating a pulsed signal (PUP) having width proportional to the lead error of the electrical pulses as to the periodical reference signal, logical circuits for generating a pulsed signal (P DOWN) having width proportional to the lag error of the electrical pulses as to the periodical reference signal (VFO), a plurality of low pass filters (7, 25-21, 26) having two poles and one zero and selectable (LFSEL) in mutually exclusive way for generating a continuous signal having variable voltage as a function of said pulsed error signals, a decoupling element (15) having the function of voltage follower for inputing the continuous signal to a variable frequency oscillator (3), temperature compensated, which generates the periodical reference signal, the selection of each one of the low pass filters determining an optimized frequency response of the phase lock circuit for each of different working conditions defined by different nominal frequencies of information recording.
摘要翻译： 相位锁定电路，用于产生具有可变频率的周期性参考信号，该频率锁定到对应于从相对于标称频率的相位调制中记录信息的可移动磁性介质读出的信息（RD）的电脉冲序列的频率， 包括用于产生脉冲信号（PUP）的相位比较器（1），该脉冲信号（PUP）的宽度与电脉冲的周期性参考信号的引导误差成比例，用于产生具有与滞后成正比的宽度的脉冲信号（P DOWN）的逻辑电路 关于周期性参考信号（VFO）的电脉冲的误差，具有两个极点的一个低通滤波器（7,25-21,26）和一个零和可选择的（LFSEL），用于产生连续信号 具有作为所述脉冲误差信号的函数的可变电压;具有电压跟随器的功能的去耦元件（15），用于将连续信号输入到可变频率 温度补偿器，其产生周期性参考信号，每个低通滤波器的选择确定针对由不同标称信号频率信息记录定义的不同工作条件的每个不同工作条件的优化的频率响应 。
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公开(公告)号：EP0320748B1
公开(公告)日：1993-02-17
申请号：EP88120320.2
申请日：1988-12-06
发明人： Vitiello, Paolo , Bergamo, Luca
IPC分类号： H03L7/14
CPC分类号： H03L1/00 , H03L7/10 , H03L2207/06
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公开(公告)号：EP0320748A3
公开(公告)日：1989-09-13
申请号：EP88120320.2
申请日：1988-12-06
发明人： Vitiello, Paolo , Bergamo, Luca
IPC分类号： H03L7/14
CPC分类号： H03L1/00 , H03L7/10 , H03L2207/06
摘要： Self adjusting phase lock circuit in which a frequency and/or phase comparator (1) compares the frequency and/or phase of a reference signal FVCO with the frequency and/or phase of a frequency or phase modulated signal RD to generate an error signal input to an integrating network (3,4), which in turn generates an error voltage related to the frequency/phase error of the two signals, said voltage being input to the control input of a voltage controlled oscillator (2) which generates reference signal FVCO as a function of the error voltage and of an adjusting voltage received at an adjusting input, wherein self adjusting means are provided consisting in a fixed reference voltage periodically input to the oscillator control input as a substitute for the error voltage, in a source of a fixed frequency signal, periodically input to the comparator (9) as a substitute for the modulated signal, in an operational network generating from the error voltage a feedback signal (VRANGE) periodically input to the adjusting input of the oscillator (2) and hold at said input by sample and hold circuits (10,11,17), so that the adjusting voltage VRANGE is periodically adjusted in automatic way to provide to the phase lock circuit an operative condition permanently close to a nominal working point, independently of thermal drift and performance spread of the used components.
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