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公开(公告)号：EP1468423A2
公开(公告)日：2004-10-20
申请号：EP03731986.0
申请日：2003-01-17
发明人： DEHON, Andre , LIEBER, Charles, M.
IPC分类号： G11C11/34 , H03K19/177
CPC分类号： G11C13/025 , B82Y10/00 , G11C8/10 , G11C13/0023 , G11C13/003 , G11C2213/75 , G11C2213/77 , G11C2213/81 , H01L27/28 , H01L27/285 , H01L51/0508 , H01L51/0595
摘要： An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscalewires.
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公开(公告)号：EP1525586A2
公开(公告)日：2005-04-27
申请号：EP03796282.6
申请日：2003-07-24
申请人： California Institute of Technology , PRESIDENT AND FELLOWS OF HARVARD COLLEGE , Sri International , Brown University
IPC分类号： G11C13/02
CPC分类号： H01L49/00 , B82Y10/00 , G11C8/10 , G11C13/0023 , G11C13/02 , G11C13/025 , G11C2213/71 , G11C2213/77 , G11C2213/81 , H01L23/522 , H01L27/101 , H01L29/0665 , H01L29/0673 , H01L2924/0002 , Y10S977/762 , Y10S977/943 , H01L2924/00
摘要： A memory array comprising nanoscale wires (61-72) is disclosed. The nanoscale wiresare addressed by means of controllable regions (80, 82) axially and/or radiallydistributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires andmicroscale wires. In a two-dimensional emobdiment, memory locations (75) aredefined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing pointsbetween nanoscale wires located in different vertical layers.
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公开(公告)号：EP1525586B1
公开(公告)日：2007-04-25
申请号：EP03796282.6
申请日：2003-07-24
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY , PRESIDENT AND FELLOWS OF HARVARD COLLEGE , SRI International , BROWN UNIVERSITY
IPC分类号： G11C13/02
CPC分类号： H01L49/00 , B82Y10/00 , G11C8/10 , G11C13/0023 , G11C13/02 , G11C13/025 , G11C2213/71 , G11C2213/77 , G11C2213/81 , H01L23/522 , H01L27/101 , H01L29/0665 , H01L29/0673 , H01L2924/0002 , Y10S977/762 , Y10S977/943 , H01L2924/00
摘要： A memory array comprising nanoscale wires (61-72) is disclosed. The nanoscale wiresare addressed by means of controllable regions (80, 82) axially and/or radiallydistributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires andmicroscale wires. In a two-dimensional emobdiment, memory locations (75) aredefined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing pointsbetween nanoscale wires located in different vertical layers.
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公开(公告)号：EP1525585A2
公开(公告)日：2005-04-27
申请号：EP03796281.8
申请日：2003-07-24
申请人： California Institute of Technology , PRESIDENT AND FELLOWS OF HARVARD COLLEGE , Sri International , Brown University
CPC分类号： H01L49/00 , B82Y10/00 , G11C8/10 , G11C13/0023 , G11C13/02 , G11C13/025 , G11C2213/71 , G11C2213/77 , G11C2213/81 , H01L23/522 , H01L27/101 , H01L29/0665 , H01L29/0673 , H01L2924/0002 , Y10S977/762 , Y10S977/943 , H01L2924/00
摘要： A method for controlling electric conduction on nanoscale wires is disclosed.The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types.For example, a first type of controllable region can exhibit a different dopingfrom a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independentlyselected.
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