公开(公告)号：EP1243024A1

公开(公告)日：2002-09-25

申请号：EP00993755.8

申请日：2000-12-28

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMicroelectronics S.A.

发明人： DEMOLLIENS, Olivier ,  BERRUYER, Pascale ,  TROUILLER, Yorick ,  MORAND, Yves

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： The invention concerns a method for making a Damascene type interconnection structure on a semiconductor device, comprising the following steps: forming a first level of conductors in a first layer on electrical insulation and a second level of conductors in a second layer of electrical insulation, the first level conductors being spaced apart to enable, in a subsequent step, the formation of cavities between the first level conductors; eliminating the second electrical insulation level; eliminating at least partially the first electrical insulation layer to eliminate the parts of the first layer corresponding to the cavities to be formed; depositing on the resulting structure a material with low permittivity, said deposit not filling up the space between the first level conductors which have been arranged spaced apart to enable the formation of cavities.

公开(公告)号：EP1212793A1

公开(公告)日：2002-06-12

申请号：EP00962614.4

申请日：2000-09-12

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMicroelectronics S.A.

发明人： MORAND, Yves ,  GOBIL, Yveline ,  DEMOLLIENS, Olivier ,  ASSOUS, Myriam

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns a method for producing a copper connection with a copper connecting element (2) of an integrated circuit comprising a damascene structure, the connecting element (2) being coated successively with an encapsulating layer (3) and at least a dielectric material layer (4) with low dielectric constant. The method comprises the following steps: etching said dielectric material layer (4) until the encapsulating layer (3) is reached, to obtain a connection hole, opposite the connecting element; producing a protective layer (7) on the wall of the connecting hole, the protective layer preventing the dielectric layer from being contaminated by copper diffusion; etching the encapsulating layer (3), at the base of the connecting hole, in such a way as to expose the connecting element (2); filling the connecting hole with copper.

公开(公告)号：EP1346405B1

公开(公告)日：2009-11-11

申请号：EP01995728.1

申请日：2001-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMicroelectronics S.A.

发明人： FRABOULET, David ,  MARIOLLE, Denis ,  MORAND, Yves

IPC分类号： H01L21/335 ,  H01L29/76

CPC分类号： B82Y10/00 ,  H01L29/66439 ,  H01L29/7613 ,  Y10S438/962

摘要： The invention concerns a method for making a microstructure comprising an island (30) of material confined between two electrodes (32) forming tabs, the island of material having two lateral flanks parallel to and two lateral flanks perpendicular to the tabs. The invention is characterised in that the lateral flanks of the island are defined by etching at least a layer (16), called template layer, and the tabs are formed by damascening. The invention is useful for making transistors and storage units.

公开(公告)号：EP1212793B1

公开(公告)日：2006-07-26

申请号：EP00962614.4

申请日：2000-09-12

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMicroelectronics S.A.

发明人： MORAND, Yves ,  GOBIL, Yveline ,  DEMOLLIENS, Olivier ,  ASSOUS, Myriam

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention concerns a method for producing a copper connection with a copper connecting element (2) of an integrated circuit comprising a damascene structure, the connecting element (2) being coated successively with an encapsulating layer (3) and at least a dielectric material layer (4) with low dielectric constant. The method comprises the following steps: etching said dielectric material layer (4) until the encapsulating layer (3) is reached, to obtain a connection hole, opposite the connecting element; producing a protective layer (7) on the wall of the connecting hole, the protective layer preventing the dielectric layer from being contaminated by copper diffusion; etching the encapsulating layer (3), at the base of the connecting hole, in such a way as to expose the connecting element (2); filling the connecting hole with copper.

公开(公告)号：EP1346405A1

公开(公告)日：2003-09-24

申请号：EP01995728.1

申请日：2001-12-17

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMicroelectronics S.A.

发明人： FRABOULET, David ,  MARIOLLE, Denis ,  MORAND, Yves

IPC分类号： H01L21/335 ,  H01L29/76

CPC分类号： B82Y10/00 ,  H01L29/66439 ,  H01L29/7613 ,  Y10S438/962

摘要： The invention concerns a method for making a microstructure comprising an island (30) of material confined between two electrodes (32) forming tabs, the island of material having two lateral flanks parallel to and two lateral flanks perpendicular to the tabs. The invention is characterised in that the lateral flanks of the island are defined by etching at least a layer (16), called template layer, and the tabs are formed by damascening. The invention is useful for making transistors and storage units.

公开(公告)号：EP1889296A1

公开(公告)日：2008-02-20

申请号：EP06764670.3

申请日：2006-05-23

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ,  STMICROELECTRONICS SA

发明人： MORAND, Yves ,  POIROUX, Thierry ,  VINET, Maud

IPC分类号： H01L29/10 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42392

摘要： Source electrodes (3) and drain electrodes (4) are each constituted of an alternation of first layers (5) and second layers (6) made of a germanium and silicon composite. The first layers (5) have a concentration of germanium ranging from 0 % to 10 %, and the second layers (6) have a concentration of germanium ranging from 10 % to 50 %. At least one channel (1) connects two second layers (6a, 6b), respectively, of the source electrodes (3) and drain electrodes (4). The invention involves the etching of source and drain regions connected by a narrow area, in a stack of layers (5, 6). Next, a superficial thermal oxidation of said stack is effected whereby oxidizing the silicon of the germanium and silicon composite having a concentration of germanium ranging from 10 % to 50 % and condensing the germanium Ge. The silicon oxide of the narrow area is eliminated and a gate dielectric (7) and a gate (2) are deposited on the condensed germanium of the narrow area.

公开(公告)号：EP1243024B1

公开(公告)日：2011-06-08

申请号：EP00993755.8

申请日：2000-12-28

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics S.A.

发明人： DEMOLLIENS, Olivier ,  BERRUYER, Pascale ,  TROUILLER, Yorick ,  MORAND, Yves

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： The invention concerns a method for making a Damascene type interconnection structure on a semiconductor device, comprising the following steps: forming a first level of conductors in a first layer on electrical insulation and a second level of conductors in a second layer of electrical insulation, the first level conductors being spaced apart to enable, in a subsequent step, the formation of cavities between the first level conductors; eliminating the second electrical insulation level; eliminating at least partially the first electrical insulation layer to eliminate the parts of the first layer corresponding to the cavities to be formed; depositing on the resulting structure a material with low permittivity, said deposit not filling up the space between the first level conductors which have been arranged spaced apart to enable the formation of cavities.