公开(公告)号：EP3166147A3

公开(公告)日：2017-08-16

申请号：EP16167775.2

申请日：2013-03-13

申请人： Cypress Semiconductor Corporation ,  Ramkumar, Krishnaswamy ,  Jin, Bo ,  Jenne, Fredrick

发明人： RAMKUMAR, Krishnaswamy ,  JIN, Bo ,  JENNE, Fredrick

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two gate layers separated by at least one dielectric layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.

摘要翻译： 公开了一种方法，包括：在衬底上形成表面上方的表面，该叠层包括由至少一个介电层分开的至少两个栅极层; 在所述栅极层堆叠的第一区域中形成非易失性存储器件，包括：形成从所述栅极层堆叠的顶表面延伸到所述栅极层堆叠的下表面的第一开口; 在第一开口的侧壁上形成电荷俘获层; 以及在电荷俘获层的内侧壁上形成半导体材料的薄层，并且用电荷俘获层的半导体材料的薄层与从栅极层的堆叠分离的电介质材料充分填充第一开口; 以及在栅极层堆叠的第二区域中形成MOS器件。

公开(公告)号：EP3166147A2

公开(公告)日：2017-05-10

申请号：EP16167775.2

申请日：2013-03-13

申请人： Cypress Semiconductor Corporation ,  Ramkumar, Krishnaswamy ,  Jin, Bo ,  Jenne, Fredrick

发明人： RAMKUMAR, Krishnaswamy ,  JIN, Bo ,  JENNE, Fredrick

IPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two gate layers separated by at least one dielectric layer; forming a non-volatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.

摘要翻译： 公开了一种方法，包括：在衬底上方的表面上形成包括由至少一个电介质层隔开的至少两个栅极层的栅层的堆叠; 在所述堆叠栅极层的第一区域中形成非易失性存储器件，包括：形成从所述栅极层堆叠的顶表面延伸到所述栅极层堆叠的下表面的第一开口; 在第一开口的侧壁上形成电荷捕获层; 以及在所述电荷俘获层的内侧壁上形成半导体材料的薄层，并且通过所述电荷俘获层的所述半导体材料薄层将绝缘材料基本上填充在与所述栅极层叠层隔离的介电材料上; 以及在栅极层叠层的第二区域中形成MOS器件。

公开(公告)号：EP2831916A1

公开(公告)日：2015-02-04

申请号：EP13767277.0

申请日：2013-03-08

申请人： Cypress Semiconductor Corporation ,  Jenne, Fredrick ,  Ramkumar, Krishnaswamy

发明人： JENNE, Fredrick ,  RAMKUMAR, Krishnaswamy

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7926

摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

摘要翻译： 描述了包括分离电荷俘获区域的非平面存储器件的实施例及其形成方法。 通常，该器件包括：由覆盖连接存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 覆盖所述隧道氧化物的分离电荷俘获区域，所述分离电荷俘获区域包括底部电荷俘获层和顶部电荷俘获层，所述底部电荷俘获层包括更靠近所述隧道氧化物的氮化物，其中所述底部电荷俘获层被分离 从顶部电荷俘获层通过包含氧化物的薄反隧道层。 其他实施例也被公开。

公开(公告)号：EP2831918A1

公开(公告)日：2015-02-04

申请号：EP13767491.7

申请日：2013-03-13

申请人： Cypress Semiconductor Corporation ,  Ramkumar, Krishnaswamy ,  Jin, Bo ,  Jenne, Fredrick

发明人： RAMKUMAR, Krishnaswamy ,  JIN, Bo ,  JENNE, Fredrick

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

摘要翻译： 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域上方形成MOS器件的衬垫电介质层; 从覆盖衬底的第二区域上方的表面的半导体材料薄膜形成存储器件的沟道，沟道连接存储器件的源极和漏极; 在所述第二区域上方形成覆盖所述沟道的图案化电介质叠层，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，并从衬底的第一区域去除衬垫电介质层; 同时在衬底的第一区域上方形成栅极介电层，并在电荷俘获层上方形成阻挡介电层。

公开(公告)号：EP3866199A1

公开(公告)日：2021-08-18

申请号：EP21160971.4

申请日：2013-03-13

申请人： Longitude Flash Memory Solutions Ltd. ,  Ramkumar, Krishnaswamy ,  Jin, Bo ,  Jenne, Fredrick

发明人： RAMKUMAR, Krishnaswamy ,  JIN, Bo ,  JENNE, Fredrick

IPC分类号： H01L27/11573 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423

摘要： Disclosed is a method comprising: forming above a surface on a substrate a stack of gate layers including at least two dielectric layers separated by at least one gate layer; forming a nonvolatile memory device in a first region of the stack of gate layers comprising: forming a first opening extending from a top surface of the stack of gate layers to a lower surface of the stack of gate layers; forming on sidewalls of the first opening a charge-trapping layer; and forming on inside sidewalls of the charge-trapping layer a thin layer of semiconducting material, and substantially filling the first opening with a dielectric material separated from the stack of gate layers by the thin layer of semiconducting material the charge-trapping layer; and forming a MOS devices in a second region of the stack of gate layers.

公开(公告)号：EP3534408A1

公开(公告)日：2019-09-04

申请号：EP18213110.2

申请日：2013-03-08

申请人： Cypress Semiconductor Corporation

发明人： JENNE, Fredrick ,  RAMKUMAR, Krishnaswamy

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/51 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/78

摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

公开(公告)号：EP3229276A1

公开(公告)日：2017-10-11

申请号：EP16188153.7

申请日：2013-03-18

申请人： Cypress Semiconductor Corporation

发明人： RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  LEVY, Sagy

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11573 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7926

摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunnelling layer; and form-ing a MOS device over a second region of the substrate.

摘要翻译： 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 一般而言，该方法包括：在衬底的第一区域中形成存储器件的沟道，该沟道来自覆盖衬底的表面的半导体材料，沟道连接存储器件的源极和漏极; 在与所述沟道的多个表面相邻的所述沟道上形成电荷俘获电介质叠层，其中所述电荷俘获电介质叠层包括在隧穿层上的电荷俘获层上的阻挡层; 以及在衬底的第二区域上形成MOS器件。

公开(公告)号：EP2831919A1

公开(公告)日：2015-02-04

申请号：EP13769241.4

申请日：2013-03-18

申请人： Cypress Semiconductor Corporation

发明人： RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  LEVY, Sagy

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7926

摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

公开(公告)号：EP1609178A2

公开(公告)日：2005-12-28

申请号：EP04708268.0

申请日：2004-02-04

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： BLOSSE, Alain ,  RAMKUMAR, Krishnaswamy ,  GOPALAN, Prabhuram,38623 Cherry Lane

IPC分类号： H01L21/44 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L29/4941 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/78

摘要： In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer (112'), forming a metal stack (110') over the silicon layer (112'), and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

公开(公告)号：EP2831917A1

公开(公告)日：2015-02-04

申请号：EP13767422.2

申请日：2013-03-15

申请人： Cypress Semiconductor Corporation

发明人： LEVY, Sagy ,  RAMKUMAR, Krishnaswamy ,  JENNE, Fredrick ,  GEHA, Sam

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7926

摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的通道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氧氮化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接沟道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。