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    SEMICONDUCTOR DEVICE
    6.
    发明授权
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：EP3035337B1

    公开(公告)日：2018-11-21

    申请号：EP13891587.1

    申请日：2013-08-15

    Applicant: Renesas Electronics Corporation

    Inventor： NISHIYAMA, Takayuki

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C16/16

    CPC classification number: G11C16/3459 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3454

    Abstract: A control circuit (105) controls execution of first-stage processing for increasing a threshold voltage of both or one of a first storage element (102) and a second storage element (103) until the threshold voltage of the first storage element (102) and the second storage element (103) attains to a prescribed write verify level when a request for erase of twin cell data is received. The control circuit 105 controls execution of second-stage processing for lowering a threshold voltage of the first storage element (102) and the second storage element (103) until the threshold voltage of the first storage element (102) and the second storage element (103) attains to a prescribed erase verify level after the first-stage processing is performed.

    BALANCING PROGRAMMING SPEEDS OF MEMORY CELLS IN A 3D STACKED MEMORY
    7.
    发明公开
    BALANCING PROGRAMMING SPEEDS OF MEMORY CELLS IN A 3D STACKED MEMORY 有权
    平衡三维堆叠存储器中存储器单元的编程速度

    公开(公告)号：EP3262655A1

    公开(公告)日：2018-01-03

    申请号：EP16728202.9

    申请日：2016-05-31

    Applicant: SanDisk Technologies LLC

    Inventor： MUI, Man L. ,  SUN, Yongke ,  DONG, Yingda

    IPC: G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2211/5621

    Abstract: Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.

    PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS
    9.
    发明公开
    PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS 审中-公开
    编程漏极字线以减少程序干扰和电荷损失

    公开(公告)号：EP3204948A1

    公开(公告)日：2017-08-16

    申请号：EP15781183.7

    申请日：2015-09-21

    Applicant: SanDisk Technologies LLC

    Inventor： YUAN, Jiahui ,  DONG, Yingda ,  LU, Ching-Huang ,  ZHAO, Wei

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.

    Abstract translation: 提供用于在对该组中的任何其他字线的存储器单元进行编程之前对该组字线的漏极侧边缘字线的存储器单元进行编程的技术。 施加到其他字线的通过电压充当应力脉冲，其重新分布其他字线的存储器单元的电荷俘获材料中的空穴以减少短时电荷损失和降低阈值电压的递减。 另外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低，并且还用作应力脉冲。 漏极侧边缘字线的存储器单元被编程为比其他字线的存储器单元更窄的Vth窗口。 这补偿了由于减小的沟道升压导致的漏极侧边缘字线的擦除状态存储器单元的较高水平的编程干扰。

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