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公开(公告)号：EP0923277A3
公开(公告)日：2000-12-06
申请号：EP98304966.9
申请日：1998-06-24
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H05K1/023 , H05K1/025 , H05K2201/10022 , H05K2201/1053 , H05K2201/10689
摘要： The invention provides a printed circuit board including a terminating structure wherein impedance matching can be established with certainty also for a long wiring line without using a discrete part as a terminating resistor. In the terminating structure, an internal wiring line (11) connected to a signal output terminal (12) of a semiconductor unit (2A) is formed with a resistance value which satisfies an impedance matching condition of a printed circuit board wiring line (13) connected to the signal output terminal (12). The terminating structure is applied to any application wherein impedance matching of a wiring line is established on a printed circuit board on which a semiconductor unit having an internal wiring line having a resistance higher than that of a wiring line on the printed circuit board is mounted.
摘要翻译： 本发明提供了一种印刷电路板，其包括端接结构，其中阻抗匹配可确定地建立在长线路上，而不使用离散部分作为终端电阻。 在端接结构中，形成连接到半导体单元（2A）的信号输出端子（12）的内部布线（11），其电阻值满足印刷电路板布线（13）的阻抗匹配条件， 连接到信号输出端子（12）。 终端结构适用于在其上安装有具有比印刷电路板上的布线的电阻高的内部布线的半导体单元的印刷电路板上建立布线的阻抗匹配的任何应用。
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公开(公告)号：EP1768261B1
公开(公告)日：2014-09-03
申请号：EP06026674.9
申请日：2004-11-08
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
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公开(公告)号：EP1768260B1
公开(公告)日：2014-09-03
申请号：EP06026673.1
申请日：2004-11-08
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
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公开(公告)号：EP0923277B1
公开(公告)日：2007-04-11
申请号：EP98304966.9
申请日：1998-06-24
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H05K1/023 , H05K1/025 , H05K2201/10022 , H05K2201/1053 , H05K2201/10689
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公开(公告)号：EP1768261A1
公开(公告)日：2007-03-28
申请号：EP06026674.9
申请日：2004-11-08
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
摘要： A clock adjustment apparatus delays a clock signal and adjusts a phase of the signal, thereby increasing or decreasing a delay amount of the clock signal in accordance with a phase relation between a data signal and an adjusted clock signal. The adjusted clock signal is used for receiving the data signal.
摘要翻译： 时钟调节装置延迟时钟信号并调节信号的相位，从而根据数据信号和调节后的时钟信号之间的相位关系增加或减少时钟信号的延迟量。 调整后的时钟信号用于接收数据信号。
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公开(公告)号：EP1608072B1
公开(公告)日：2014-09-03
申请号：EP04256897.2
申请日：2004-11-08
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
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7.发明公开
公开(公告)号：EP1768260A1
公开(公告)日：2007-03-28
申请号：EP06026673.1
申请日：2004-11-08
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H03L7/0814 , H03L7/091 , H03L7/093
摘要： A clock adjustment apparatus delays a clock signal and adjusts a phase of the signal, thereby increasing or decreasing a delay amount of the clock signal in accordance with a phase relation between a data signal and an adjusted clock signal. The adjusted clock signal is used for receiving the data signal.
摘要翻译： 时钟调整装置延迟时钟信号并调整信号的相位，从而根据数据信号和调整后的时钟信号之间的相位关系增加或减少时钟信号的延迟量。 调整后的时钟信号用于接收数据信号。
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公开(公告)号：EP0923277A2
公开(公告)日：1999-06-16
申请号：EP98304966.9
申请日：1998-06-24
申请人： FUJITSU LIMITED
发明人： Yamada, Jun
CPC分类号： H05K1/023 , H05K1/025 , H05K2201/10022 , H05K2201/1053 , H05K2201/10689
摘要： The invention provides a printed circuit board including a terminating structure wherein impedance matching can be established with certainty also for a long wiring line without using a discrete part as a terminating resistor. In the terminating structure, an internal wiring line (11) connected to a signal output terminal (12) of a semiconductor unit (2A) is formed with a resistance value which satisfies an impedance matching condition of a printed circuit board wiring line (13) connected to the signal output terminal (12). The terminating structure is applied to any application wherein impedance matching of a wiring line is established on a printed circuit board on which a semiconductor unit having an internal wiring line having a resistance higher than that of a wiring line on the printed circuit board is mounted.
摘要翻译： 本发明提供了一种包括终端结构的印刷电路板，其中对于长布线而言也可以确定阻抗匹配，而不使用分立部件作为终端电阻器。 在端接结构中，连接到半导体单元（2A）的信号输出端子（12）的内部布线（11）形成有满足印刷电路板布线（13）的阻抗匹配条件的电阻值， 连接到信号输出端子（12）。 终端结构适用于其上安装具有电阻高于印刷电路板上的布线的内部布线的半导体单元的印刷电路板上的布线的阻抗匹配的任何应用。
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