OPTICAL TRANSCEIVER AND HOST ADAPTER WITH MEMORY MAPPED MONITORING CIRCUITRY
    2.
    发明授权
    OPTICAL TRANSCEIVER AND HOST ADAPTER WITH MEMORY MAPPED MONITORING CIRCUITRY 有权
    具有存储器映射监控电路的光收发器和主机适配器

    公开(公告)号:EP1747624B1

    公开(公告)日:2018-02-14

    申请号:EP05737559.4

    申请日:2005-04-20

    IPC分类号: H04B10/079 H04B10/50

    摘要: A host adaptor is configured to monitor operation of an optoelectronic transceiver. The host adapter includes a transceiver interface, memory, comparison logic and a host interface. The transceiver interface receives from the optoelectronic transceiver digital values corresponding to operating conditions of the optoelectronic transceiver. The memory includes one or more memory arrays for storing information related to the optoelectronic transceiver, including the digital values received from the optoelectronic transceiver. The comparison logic is configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic transceiver. The host interface enables a host device to read from host specified locations within the memory, including the predefined flag storage locations, in accordance with commands received from the host device.

    OPTICAL TRANSCEIVER AND HOST ADAPTER WITH MEMORY MAPPED MONITORING CIRCUITRY
    3.
    发明公开
    OPTICAL TRANSCEIVER AND HOST ADAPTER WITH MEMORY MAPPED MONITORING CIRCUITRY 有权
    光发射器/接收器和主机适配器内存监控电路

    公开(公告)号:EP1747624A1

    公开(公告)日:2007-01-31

    申请号:EP05737559.4

    申请日:2005-04-20

    IPC分类号: H04B10/08

    摘要: A host adaptor is configured to monitor operation of an optoelectronic transceiver. The host adapter includes a transceiver interface, memory, comparison logic and a host interface. The transceiver interface receives from the optoelectronic transceiver digital values corresponding to operating conditions of the optoelectronic transceiver. The memory includes one or more memory arrays for storing information related to the optoelectronic transceiver, including the digital values received from the optoelectronic transceiver. The comparison logic is configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic transceiver. The host interface enables a host device to read from host specified locations within the memory, including the predefined flag storage locations, in accordance with commands received from the host device.

    INTEGRATED MEMORY CONTROLLER CIRCUIT FOR FIBER OPTICS TRANSCEIVER
    4.
    发明授权
    INTEGRATED MEMORY CONTROLLER CIRCUIT FOR FIBER OPTICS TRANSCEIVER 有权
    整合速度快速发送器/EMPFÄNGERFÜRFASER

    公开(公告)号:EP1360782B1

    公开(公告)日:2007-03-28

    申请号:EP02704344.7

    申请日:2002-02-04

    摘要: A controller (110) for controlling a transceiver having a laser transmitter and a photodiode receiver. The controller includes memory (120, 122, 128) for storing information related to the transceiver, and analog to digital conversion circuitry (127) for receiving a plurality of analog signals from the laser transmitter and photodiode receiver, converting the received analog signals into digital values, and storing the digital values in predefined locations within the memory. Comparison logic (131) compares one or more of these digital values with limit values, generates flag values based on the comparisons, and stores the flag values in predefined locations within the memory. Control circuitry (123-1, 123-2) in the controller controls the operation of the laser transmitter in accordance with one or more values stored in the memory. A serial interface (121) is provided to enable a host device to read from and write to locations within the memory. Excluding a small number of binary input and output signals, all control and monitoring functions of the transceiver are mapped to unique memory mapped locations within the controller. A plurality of the control functions and a plurality of the monitoring functions of the controller are exercised by a host computer by accessing corresponding memory mapped locations within the controller.

    摘要翻译: 一种用于控制具有激光发射器和光电二极管接收器的收发器的控制器(110)。 控制器包括用于存储与收发器有关的信息的存储器(120,122,128),以及用于从激光发射器和光电二极管接收器接收多个模拟信号的模数转换电路(127),将接收的模拟信号转换为数字 值,并将数字值存储在存储器内的预定位置中。 比较逻辑(131)将这些数字值中的一个或多个与限制值进行比较,基于比较生成标志值,并将该标志值存储在存储器内的预定位置中。 控制电路(123-1,123-2)根据存储在存储器中的一个或多个值控制激光发射器的操作。 提供串行接口(121)以使得主机设备能够从存储器内的位置读取和写入。 排除少量的二进制输入和输出信号,收发器的所有控制和监视功能都映射到控制器内唯一的内存映射位置。 控制器的多个控制功能和多个监控功能由主机通过访问控制器内的对应存储器映射位置来执行。

    APPARATUS FOR ENHANCING IMPEDANCE-MATCHING IN A HIGH-SPEED DATA COMMUNICATIONS SYSTEM
    5.
    发明公开
    APPARATUS FOR ENHANCING IMPEDANCE-MATCHING IN A HIGH-SPEED DATA COMMUNICATIONS SYSTEM 审中-公开
    设备技术改进阻抗匹配在高数据通信系统

    公开(公告)号:EP1518260A2

    公开(公告)日:2005-03-30

    申请号:EP03738875.8

    申请日:2003-03-19

    IPC分类号: H01L21/00

    摘要: An impedance-matching electrical connection system (400), for use with high-frequency communication signals, includes a circuit board and a plurality of contact pads (404-4, 404-2) mounted on the circuit board. The contact pads are for coupling with a plurality of complementary connectors of an external electrical device. Each coupling is associated with an excess shunt capacitance. The electrical connection system further includes a plurality of inductive traces (408-n) mounted on the circuit board, each of which is connected to a respective contact pad, and is associated with a compensating series inductance. Additionally, the electrical connection system includes a plurality of signal lines (406-1) mounted on the circuit board, each of which is connected to a respective inductive trace. Each inductive trace is configured so that its associated compensating series inductance substantially offsets the excess shunt capacitance associated with the coupling between the contact pad connected to the inductive trace and a complementary connector.

    INTEGRATED MEMORY CONTROLLER CIRCUIT FOR FIBER OPTICS TRANSCEIVER
    6.
    发明公开
    INTEGRATED MEMORY CONTROLLER CIRCUIT FOR FIBER OPTICS TRANSCEIVER 有权
    集成了内存控制电路发送器/接收器纤维

    公开(公告)号:EP1360782A1

    公开(公告)日:2003-11-12

    申请号:EP02704344.7

    申请日:2002-02-04

    IPC分类号: H04B10/00

    摘要: A controller (110) for controlling a transceiver having a laser transmitter and a photodiode receiver. The controller includes memory (120, 122, 128) for storing information related to the transceiver, and analog to digital conversion circuitry (127) for receiving a plurality of analog signals from the laser transmitter and photodiode receiver, converting the received analog signals into digital values, and storing the digital values in predefined locations within the memory. Comparison logic (131) compares one or more of these digital values with limit values, generates flag values based on the comparisons, and stores the flag values in predefined locations within the memory. Control circuitry (123-1, 123-2) in the controller controls the operation of the laser transmitter in accordance with one or more values stored in the memory. A serial interface (121) is provided to enable a host device to read from and write to locations within the memory. Excluding a small number of binary input and output signals, all control and monitoring functions of the transceiver are mapped to unique memory mapped locations within the controller. A plurality of the control functions and a plurality of the monitoring functions of the controller are exercised by a host computer by accessing corresponding memory mapped locations within the controller.

    ANALOG TO DIGITAL SIGNAL CONDITIONING IN OPTOELECTRONIC TRANSCEIVERS
    8.
    发明公开
    ANALOG TO DIGITAL SIGNAL CONDITIONING IN OPTOELECTRONIC TRANSCEIVERS 审中-公开
    模拟到数字信号处理光电SENDER器/接收器

    公开(公告)号:EP1738501A1

    公开(公告)日:2007-01-03

    申请号:EP05745644.4

    申请日:2005-04-01

    IPC分类号: H04B10/08 H04B10/28

    摘要: Circuitry for monitoring the operation of an optoelectronic transceiver includes a sequence of interconnected signal processing circuits for processing an analog input signal and producing a digital result signal, where the analog signal represents one or more operating conditions of the optoelectronic transceiver. The sequence of signal processing circuits include gain circuitry for amplifying or attenuating the analog input signal by a gain value to produce a scaled analog signal, an analog to digital converter for converting the scaled analog signal into a first digital signal, and digital adjustment circuitry for digitally adjusting the first digital signal to produce the digital result signal. The digital adjustment circuitry includes shifting circuitry configured to shift an input digital signal in accordance with a shift value so as to produce a digital shifted signal. The digital result signal is stored in memory in predefined locations accessible by a host.

    OPTICAL TRANSCEIVER MODULE WITH MULTIPURPOSE INTERNAL SERIAL BUS
    9.
    发明公开
    OPTICAL TRANSCEIVER MODULE WITH MULTIPURPOSE INTERNAL SERIAL BUS 审中-公开
    光发射机/EMPFûNGERMODUL与内部串行MEHRZWECKBUS

    公开(公告)号:EP1550244A2

    公开(公告)日:2005-07-06

    申请号:EP03773210.4

    申请日:2003-10-08

    IPC分类号: H04B10/00

    摘要: The optical transceiver module includes an optical transmitter and an optical receiver. The optical transceiver module also includes an internal serial bus and a plurality of addressable components electrically coupled to the internal serial bus. Each of the addressable components included a serial interface for communicating with the internal serial bus, and a memory. Each addressable component also includes a unique address or chip select logic coupled to a controller via a chip select line. This allows data to be addressed to specific addressable components. The addressable components may include a laser driver, a laser bias controller, a power controller, a pre-amplifier, a post-amplifier, a laser wavelength controller, a main controller, a electrothermal cooler, an analog-to-digital converter, a digital-to-analog converter, an APD bias controller, or any combination of the aforementioned components.

    RECEPTACLE WITH MULTIPLE CONTACT SETS EACH FOR DIFFERENT CONNECTOR TYPES
    10.
    发明公开
    RECEPTACLE WITH MULTIPLE CONTACT SETS EACH FOR DIFFERENT CONNECTOR TYPES 审中-公开
    具有多接触式记录组,每组针对不同类型的连接器

    公开(公告)号:EP2195889A2

    公开(公告)日:2010-06-16

    申请号:EP08831677.3

    申请日:2008-09-17

    IPC分类号: H01R13/648

    摘要: A receptacle that is configured to receive connectors of different types. If a connector of one type is received into the receptacle, the connector contacts engage one set of receptacle contacts. If a connector of another type is received into the receptacle, the connector contacts engage another set of receptacle contacts, and so forth for potentially other connector types and other contact sets. A communication system may also control which PHY circuitry communicates with the receptacle depending on which connector type is plugged into the receptacle.