公开(公告)号：EP3295770A1

公开(公告)日：2018-03-21

申请号：EP16723288

申请日：2016-05-02

Applicant: PHILIPS LIGHTING HOLDING BV

Inventor： HAGELAAR JORIS HUBERTUS ANTONIUS ,  VROEGOP AART JAN

IPC: H05B33/08 ,  F21S4/00 ,  F21V5/00 ,  H05K1/18

CPC classification number: H05B33/0803 ,  H05B33/0821 ,  H05K1/025 ,  H05K1/189 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10106

Abstract: The present invention provides a light emitting diode(s), LED, light strip arranged for providing improved color consistency over its length. The LED light strip comprises LED strings positioned along the length of the LED light strip and powered in parallel, for emitting, for example, red, green, blue and white light. The resistance of the supply and return traces, in combination with variations in the current drawn by or the forward voltage of the various LED and resistors used in the LED strings of different color, causes a voltage drop along these traces leading to inconsistent color rendering. By adjusting the resistivity of the traces, such as through providing return paths having different resistances for LED strings of different color, the consistency of the color rendering can be improved.

公开(公告)号：EP3229564A1

公开(公告)日：2017-10-11

申请号：EP16163665.9

申请日：2016-04-04

Applicant: SICK AG

Inventor： Birkle, Stefan ,  Reichenbach, Hans-Peter

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/111 ,  H05K1/117 ,  H05K1/14 ,  H05K3/3442 ,  H05K3/366 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2203/046 ,  Y02P70/611

Abstract: Leiterplattenanordnung mit mindestens zwei senkrecht zueinander stehenden Leiterplatten (2, 8), wobei eine erste Leiterplatte (2) an einer Seite (4) an einer Leiterplattenkante (3) erste Kontaktflächen (6) aufweist, wobei eine zweite Leiterplatte (8) auf einer Seite (4) zweite Kontaktflächen (10) aufweist, wobei die zweiten Kontaktflächen (10) der zweiten Leiterplatte (8) senkrecht liegend an den ersten Kontaktflächen (6) der ersten Leiterplatte (2) angeordnet sind und die ersten Kontaktflächen (6) der ersten Leiterplatte (2) mit den zweiten Kontaktflächen (10) der zweiten Leiterplatte (8) elektrisch mittels Lötmittel (5) verbunden sind, wobei die Kontaktflächen (6, 10) einer Leiterplatte (2, 8) entlang einer Verbindungsstelle (11) zur anderen Leiterplatte (3) überstehend zu gegenüberliegenden Kontaktflächen (10, 6) der gegenüberliegenden Leiterplatte (8, 2) sind und mindestens die Kontaktflächen (6, 10) einer Leiterplatte (2, 8) sich in Richtung der Verbindungsstelle (11) verjüngen oder verkleinern.

Abstract translation: 具有至少两个互相垂直的印刷电路板的电路板组件（2，8），其中，第一电路板（2）在一侧（4）到电路板的边缘（3）的第一接触表面（6），其中的第二电路板（8）上的一个侧 （4）具有第二接触表面（10），所述第二电路板的第二接触表面（10）（8）被布置垂直位于第一接触表面（6）的第一印刷电路板（2）与所述第一接触表面（6）的所述第一电路基板上 （2）通过焊料（5），其中，所述接触面（6，10）的电路板沿接合处（11）（2,8）的装置（其他印制电路板连接到第二电路板（8）电的第二接触表面（10） 3）站立在相对的接触表面（10，6）相对的电路板（8，2）和至少接触面（6，10）的电路板（2,8）延伸（朝向连接点11） 重新振兴或缩小。

公开(公告)号：EP3201964A1

公开(公告)日：2017-08-09

申请号：EP14903089.2

申请日：2014-09-29

Applicant: LG Display Co., Ltd.

Inventor： ZHANG, Zhen ,  DRZAIC, Paul, Stephen ,  KWON, Seyeoul ,  YOUN, Sangcheon ,  YANG, Heeseok ,  LEE, Chanwoo ,  JO, Soyoung ,  HA, Anna ,  KIM, Dongyoon ,  LEE, Saemleenuri ,  CHO, Yoondong

IPC: H01L51/56

CPC classification number: H04M1/0268 ,  G06F1/1652 ,  G09F9/301 ,  H01L27/3276 ,  H01L51/0097 ,  H01L51/56 ,  H01L2251/5338 ,  H05K1/028 ,  H05K1/0283 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/10128

Abstract: A conductive trace design is described that minimizes the possibility of crack initiation and propagation in conductive traces during bending. The conductive trace design has a winding trace pattern that is more resistant to the formation of cracks at high stress points in the conductive traces. The conductive trace design includes a cap that helps ensure electrical connection of the conductive trace even though one or more cracks may begin to form in the conductive portion of the conductive trace.

公开(公告)号：EP3090609B1

公开(公告)日：2017-06-28

申请号：EP14812556.0

申请日：2014-12-17

Applicant: Philips Lighting Holding B.V.

Inventor： DE VAAN, Adrianus Johannes Stephanus Maria ,  PEELS, Wilhelmus Gerardus Maria ,  DEEBEN, Josephus Paulus Augustinus

IPC: H05K3/44 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/12 ,  H05K1/05 ,  H05K3/32

CPC classification number: H05K3/32 ,  H05K1/0284 ,  H05K1/056 ,  H05K1/092 ,  H05K3/0014 ,  H05K3/0061 ,  H05K3/1216 ,  H05K3/125 ,  H05K3/321 ,  H05K3/44 ,  H05K2201/0129 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10106 ,  H05K2201/10113 ,  H05K2203/1461

公开(公告)号：EP2833704A4

公开(公告)日：2016-01-06

申请号：EP13769962

申请日：2013-03-27

Applicant: FUJIKURA LTD

Inventor： MATSUMARU KOHEI

IPC: H05K1/02

CPC classification number: H01P3/026 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/0271 ,  H05K1/0274 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10121

Abstract: A wiring board including: a board; a differential transmission line which is constituted by two wirings disposed on the board in parallel; an insulation resin layer which is formed on part of a face of the board, wherein a stepped portion constituted by a lateral face of the insulation resin layer is formed at a boundary between the face of the board and a top face of the insulation resin layer, the two wirings extend from the face of the board to the top face of the insulation resin layer so as to traverse the stepped portion, and the extending direction of the wirings traversing the stepped portion and the direction of a periphery are perpendicular to each other in a plan view of the board, the periphery being defined by a boundary between the top face of the insulation resin layer and the lateral face of the insulation resin layer constituting the stepped portion.

公开(公告)号：EP2907191A1

公开(公告)日：2015-08-19

申请号：EP13847868.0

申请日：2013-08-08

Applicant: Raytheon Company

Inventor： BROWN, Andrew K. ,  OBERT, Thomas L. ,  SOTELO, Michael J. ,  GRITTERS, Darin M. ,  BROWN, Kenneth W.

IPC: H01P1/162

CPC classification number: H05K1/167 ,  H05K1/0234 ,  H05K1/0242 ,  H05K3/06 ,  H05K2201/0379 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09781

Abstract: An apparatus for conveying an electrical signal includes: a conductive pathway having a conductive material. The conductive material has a first edge and a second edge and is configured to convey the electrical signal. The apparatus also includes a resistive material in contact with at least a portion of the conductive pathway, covering an edge of the conductive pathway, and extending beyond the edge. The resistive material has a conductivity less than the conductivity of the conductive material.

公开(公告)号：EP2870836A1

公开(公告)日：2015-05-13

申请号：EP13734572.4

申请日：2013-06-19

Applicant: Cisco Technology, Inc.

Inventor： MANTIPLY, Paul, L.

IPC: H05K1/02 ,  H05K1/16 ,  H01L23/66 ,  H01P5/02

CPC classification number: H05K1/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15311 ,  H03H7/38 ,  H05K1/0231 ,  H05K1/0245 ,  H05K1/162 ,  H05K2201/09727 ,  H01L2924/00

Abstract: A transmission line is provided in which a first portion of the transmission line is configured to be connected to a source, and a second portion of the transmission line is configured to be connected to a load. A capacitive element is coupled to the transmission line and is configured to compensate for an impedance difference between the load and at least one of the source or the transmission line, at a frequency within a frequency bandwidth of the load. A difference between an internal capacitance of the first portion of the transmission line and the second portion of the transmission line substantially matches the capacitance of the capacitive element.

公开(公告)号：EP2849543A1

公开(公告)日：2015-03-18

申请号：EP13184042.3

申请日：2013-09-12

Applicant: Fujitsu Semiconductor Limited

Inventor： Dedic, Ian Juso

IPC: H05K1/02 ,  H01P11/00 ,  H01P1/22 ,  H01L23/64

CPC classification number: H01P1/268 ,  H01L23/64 ,  H01L2924/0002 ,  H01P1/22 ,  H01P1/227 ,  H01P11/003 ,  H03H7/383 ,  H05K1/0219 ,  H05K1/0246 ,  H05K1/025 ,  H05K2201/09727 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A lossy electrical-signal transmission line having first and second ends, the transmission line being configured such that: its characteristic impedance at the first end has a first value; its characteristic impedance at the second end has a second value, lower than the first value; and its series resistance measured from its first end to its second end is within a given range of the difference between said first and second values.

Abstract translation: 一种具有第一和第二端的有损耗的电信号传输线，所述传输线被配置为使得其第一端的特征阻抗具有第一值; 其在第二端的特征阻抗具有低于第一值的第二值; 并且其从其第一端到其第二端测量的串联电阻在所述第一值和第二值之间的差的给定范围内。

公开(公告)号：EP1465469B1

公开(公告)日：2014-04-09

申请号：EP04011727.7

申请日：1996-08-30

Applicant: Panasonic Corporation

Inventor： Takahashi, Ken ,  Chikahisa, Naoichi ,  Nagasawa, Yousuke ,  Naito, Takao ,  Wachi, Akihiko ,  Yanachi, Seishiro ,  Nagafuku, Nobuyasu ,  Kakishima, Nobuyuki

IPC: H05K3/34

CPC classification number: B41F15/0818 ,  H05K3/1233 ,  H05K3/3484 ,  H05K2201/09727 ,  H05K2203/0139 ,  H05K2203/0264 ,  H05K2203/0783 ,  H05K2203/163

公开(公告)号：EP2667690A2

公开(公告)日：2013-11-27

申请号：EP12168996.2

申请日：2012-05-23

Applicant: Tyco Electronics Belgium EC BVBA ,  Tyco Electronics Nederland B.V.

Inventor： Decrock, Lieven ,  Smink, Rutger ,  Van het Bolscher, Han ,  Campschroer, Dolf ,  Van Gils, Wijnand

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H01R12/721 ,  H01R12/728 ,  H05K1/025 ,  H05K1/117 ,  H05K3/0061 ,  H05K3/4641 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/09145 ,  H05K2201/09618 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2201/10356

Abstract: The invention relates to a three-dimensional circuit board (1), comprising a carrier component (10; 30), carrying at least one circuit path (110, 120) at an outside of a carrier body (100; 300) of the carrier component (10; 30), wherein, for impedance control, the carrier body (100; 300) comprises a deepening (102), wherein the circuit path (110, 120) is at least partially arranged in the deepening (102).

Abstract translation: 本发明涉及一种三维电路板（1），其包括载体部件（10; 30），其在载体的载体主体（100; 300）的外侧承载至少一个电路路径（110,120） 其特征在于，为了阻抗控制，载体主体（100; 300）包括深化（102），其中电路路径（110,120）至少部分地布置在深化（102）中。