公开(公告)号：EP2577422A2

公开(公告)日：2013-04-10

申请号：EP11787069.1

申请日：2011-04-20

Applicant: Freescale Semiconductor, Inc.

Inventor： RAMARAJU, Ravindraraj ,  BEARDEN, David, R. ,  COOPER, Troy, L.

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/171

Abstract: A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.

公开(公告)号：EP2502233A2

公开(公告)日：2012-09-26

申请号：EP10831941.9

申请日：2010-09-23

Applicant: Freescale Semiconductor, Inc.

Inventor： GUPTA, Ravi ,  BEARDEN, David R. ,  RAMARAJU, Ravindraraj

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/1006 ,  G11C7/1075 ,  G11C7/18 ,  G11C19/00 ,  G11C19/28

Abstract: An array (10) of memory bit cells (20) are operable to provide a memory device (930) having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array (940) can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.