公开(公告)号：EP2047504A2

公开(公告)日：2009-04-15

申请号：EP07870952.4

申请日：2007-04-24

申请人： Freescale Semiconductor, Inc.

发明人： RAO, Rajesh A. ,  LUO, Tien Ying ,  MURALIDHAR, Ramachandran ,  STEIMLE, Robert F ,  STRAUB, Sherry G.

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L21/32134 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

摘要： A method of making a semiconductor device includes a substrate (12) having a semiconductor layer (12) having a first portion (16) for non-volatile memory and a second portion (18) exclusive of the first portion (16). A first dielectric layer (14) is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters (20) is formed over the first portion and a second plurality of nanoclusters (28) over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer (38) is formed over the semiconductor layer. A conductive layer (40) is formed over the second dielectric layer.

公开(公告)号：EP2126977A1

公开(公告)日：2009-12-02

申请号：EP08729518.4

申请日：2008-02-11

申请人： Freescale Semiconductor, Inc.

发明人： RAO, Rajesh A. ,  MURALIDHAR, Ramachandran

IPC分类号： H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： An electronic device including a nonvolatile memory cell can include a substrate (10) including a first portion and a second portion, wherein a first major surface (111) within the first portion lies at an elevation lower than a second major surface (113) within the second portion. The electronic device can also include a charge storage stack (12) overlying the first portion, wherein the charge storage stack (12) includes discontinuous storage elements. The electronic device can further include a control gate electrode (24) overlying the first portion, and a select gate electrode (94) overlying the second portion, wherein the select gate electrode (94) includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack (12) and control gate electrode (24). A semiconductor layer (40) can be formed after the charge storage stack (12) and control gate electrode (94) are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode (94) can be formed over the semiconductor layer (40).

公开(公告)号：EP1844492B1

公开(公告)日：2010-07-07

申请号：EP05854006.3

申请日：2005-12-14

申请人： Freescale Semiconductor, Inc.

发明人： RAO, Rajesh A. ,  MURALIDHAR, Ramachandran ,  WHITE, Bruce E.

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/42348 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/518

摘要： A nanocrystal non-volatile memory (NVM) (10) has a dielectric (22) between the control gate (26) and the nanocrystals (16) that has a nitrogen content sufficient to reduce the locations in the dielectric (22) where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals (16) where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate (26) where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.

公开(公告)号：EP1844492A2

公开(公告)日：2007-10-17

申请号：EP05854006.3

申请日：2005-12-14

申请人： Freescale Semiconductor, Inc.

发明人： RAO, Rajesh A. ,  MURALIDHAR, Ramachandran ,  WHITE, Bruce E.

IPC分类号： H01L21/331

CPC分类号： H01L29/42348 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/518

摘要： A nanocrystal non-volatile memory (NVM) (10) has a dielectric (22) between the control gate (26) and the nanocrystals (16) that has a nitrogen content sufficient to reduce the locations in the dielectric (22) where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals (16) where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate (26) where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.