公开(公告)号：EP1936630A1

公开(公告)日：2008-06-25

申请号：EP07112380.6

申请日：2007-07-12

申请人： Fujitsu Ltd.

发明人： Kawakubo, Tomohiro c/o FUJITSU LIMITED ,  Yamaguchi, Syusaku c/o FUJITSU LIMITED ,  Ikeda, Hitoshi c/o FUJITSU LIMITED ,  Uchida, Toshiya c/o FUJITSU LIMITED ,  Kobayashi, Hiroyuki c/o FUJITSU LIMITED ,  Kanda, Tatsuya c/o FUJITSU LIMITED ,  Yamamoto, Yoshinobu c/o FUJITSU LIMITED ,  Shirakawa, Satoru c/o FUJITSU LIMITED ,  Miyamoto, Tetsuo c/o FUJITSU LIMITED ,  Otsuka, Tatsushi c/o FUJITSU LIMITED ,  Takahashi, Hidenaga c/o FUJITSU LIMITED ,  Kurita, Masanori c/o FUJITSU LIMITED ,  Kamata, Shinnosuke c/o FUJITSU LIMITED ,  Sato, Ayako c/o FUJITSU LIMITED

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供一种存储器件，存储器件的存储器控​​制器及其存储器系统，其中由存储器件的刷新操作引起的有效带宽的减少已经得到解决。 响应于来自存储器控制器的命令而操作的存储器件具有多个存储体，这些存储体分别具有包括存储器单元阵列和解码器的存储器核并且通过存储体地址来选择; 以及控制电路，其响应于后台刷新命令，使由存储器控制器设置的刷新目标存储体内的存储器内核连续执行与由存储控制器设置的刷新突发长度相对应的刷新操作次数， 并且响应于正常操作命令，在由存储器核执行的刷新操作期间，进一步使除了刷新目标存储体之外的存储体内的存储器核以及由存储体地址选择的存储器核执行与正常操作命令对应的正常存储器操作 在刷新目标银行内。

公开(公告)号：EP1898422A1

公开(公告)日：2008-03-12

申请号：EP07113892.9

申请日：2007-08-06

申请人： Fujitsu Ltd.

发明人： Kobayashi, Hiroyuki c/o FUJITSU LIMITED

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C7/02 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2227

摘要： A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line at least during a standby period when the memory cell is not accessed. A substrate voltage of an nMOS transistor with source or drain connected to the bit line is set to the low level voltage or lower of the word line. Therefore, when the word line and the bit line fails short and the voltage of the bit line changes to the low level voltage of the word line during the standby period, a substrate current can be prevented from flowing between the source of the nMOS transistor and a substrate or the drain and the substrate.

摘要翻译： 当存储单元被访问时，字驱动器向字线提供高电平电压，并且当存储单元未被访问时向字线提供作为负电压的低电平电压。 至少在未访问存储器单元的待机期间，预充电电路降低对位线的预充电电压供应容量。 源极或漏极连接到位线的nMOS晶体管的衬底电压被设置为字线的低电平电压或更低电压。 因此，在待机期间，当字线和位线失效并且位线的电压变为字线的低电平电压时，可以防止衬底电流在nMOS晶体管的源极和 衬底或漏极和衬底。

公开(公告)号：EP1936628A1

公开(公告)日：2008-06-25

申请号：EP07112384.8

申请日：2007-07-12

申请人： Fujitsu Ltd.

发明人： Ikeda, Hitoshi c/o FUJITSU LIMITED ,  Sato, Takahiko c/o FUJITSU LIMITED ,  Kanda, Tatsuya c/o FUJITSU LIMITED ,  Uchida, Toshiya c/o FUJITSU LIMITED ,  Kobayashi, Hiroyuki c/o FUJITSU LIMITED ,  Shirakawa, Satoru c/o FUJITSU LIMITED ,  Miyamoto, Tetsuo c/o FUJITSU LIMITED ,  Yamamoto, Yoshinobu c/o FUJITSU LIMITED ,  Otsuka, Tatsushi c/o FUJITSU LIMITED ,  Takahashi, Hidenaga c/o FUJITSU LIMITED ,  Kurita, Masanori c/o FUJITSU LIMITED ,  Kamata, Shinnosuke c/o FUJITSU LIMITED ,  Sato, Ayako c/o FUJITSU LIMITED

IPC分类号： G11C8/12

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

摘要翻译： 该存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个页面区域由存储体地址选择; 行控制器，响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出终端。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和所提供的存储体地址，产生用于多个存储体的存储体激活信号，并响应于第一命令而生成多个存储体中的每一个的行地址 提供的银行地址和提供的行地址。 响应于由行地址计算器生成的存储体激活信号和行地址，多个存储体激活页面区域。