Abstract:
Each semiconductor chip of a detector comprises a semiconductor substrate having a plurality of photodetector units, an insulating layer formed on a front face of the semiconductor substrate, a common electrode arranged on the insulating layer, a readout line for electrically connecting a quenching resistance of each photodetector unit and the common electrode to each other, and a through electrode extending from the common electrode to a rear face of the semiconductor substrate through a through hole of the semiconductor substrate.
Abstract:
A p - type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n + type impurity region 23, a p + type impurity region 25, and a region to be depleted with application of a bias voltage in the p - type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p - type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p - type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
Abstract:
A semiconductor photodetection element SP has a silicon substrate 21 comprised of a semiconductor of a first conductivity type, having a first principal surface 21a and a second principal surface 21b opposed to each other, and having a semiconductor layer 23 of a second conductivity type formed on the first principal surface 21a side; and charge transfer electrodes 25 provided on the first principal surface 21a and adapted to transfer generated charge. In the silicon substrate 21, an accumulation layer 31 of the first conductivity type having a higher impurity concentration than the silicon substrate 21 is formed on the second principal surface 21b side and an irregular asperity 10 is formed in a region opposed to at least the semiconductor region 23, in the second principal surface 21b. The region where the irregular asperity 10 is formed in the second principal surface 21b of the silicon substrate 21 is optically exposed.
Abstract:
Prepared is an n - type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p + type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p + type semiconductor region 3 in the second principal surface 1a of the n - type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n - type semiconductor substrate 1 is formed on the second principal surface 1a side of the n - type semiconductor substrate 1. After formation of the accumulation layer 11, the n - type semiconductor substrate 1 is subjected to a thermal treatment.