公开(公告)号：EP4429119A2

公开(公告)日：2024-09-11

申请号：EP24171288.4

申请日：2012-10-10

Applicant: Sony Group Corporation

Inventor： NAGAI, Toshiaki ,  KOSEKI, Ken ,  UENO, Yosuke ,  SUZUKI, Atsushi

IPC: H03M1/08 ,  H03M1/12 ,  H03M1/56 ,  H01L27/146

CPC classification number: H03M1/56 ,  H03M1/0863 ,  H03M1/123 ,  H01L27/14618 ,  H01L2924/000220130101 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H04N25/78 ,  H04N25/621

Abstract: [Object] To provide a semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof, and eventually reducing cost.
[Solving Means] It includes a first chip 110 and a second chip 120, the first chip and the second chip being bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes 114, the first chip 110 transmitting signals obtained by time-discretizing analog signals generated by the respective sensors 111 to the second chip through the corresponding via holes, the second chip 120 having a function of sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and a function of quantizing the sampled signals to obtain digital signals.

公开(公告)号：EP3706172B1

公开(公告)日：2024-09-11

申请号：EP20166179.0

申请日：2011-07-04

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14601 ,  H01L27/14645 ,  H01L27/1469 ,  H01L27/14636 ,  H01L27/14621 ,  H01L27/14685 ,  H01L24/05 ,  H01L2224/8089620130101 ,  H01L2224/8089520130101 ,  H01L2224/8035720130101 ,  H01L2224/0812120130101 ,  H01L2224/0564720130101 ,  H01L2224/0554720130101 ,  H01L2224/0512420130101 ,  H01L2224/0564420130101 ,  H01L2224/0518120130101 ,  H01L2224/0514920130101 ,  H01L2224/0517920130101 ,  H01L2224/0517120130101 ,  H01L2224/0518620130101 ,  H01L2224/0555720130101 ,  H01L2224/0360220130101 ,  H01L2224/039120130101 ,  H01L2224/0555420130101 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0502220130101 ,  H01L2224/803420130101 ,  H01L2224/8098620130101 ,  H01L2224/0554620130101 ,  H01L2224/0814520130101

公开(公告)号：EP3783657B1

公开(公告)日：2024-05-29

申请号：EP20200078.2

申请日：2012-04-27

IPC: H01L27/146 ,  H04N25/70

CPC classification number: H01L27/14634 ,  H01L27/14636 ,  H01L27/14605 ,  H04N25/70 ,  H04N25/79 ,  H04N25/75

公开(公告)号：EP3176814B1

公开(公告)日：2024-05-01

申请号：EP16201313.0

申请日：2016-11-30

IPC: H01L21/60 ,  H01L27/146 ,  H01L21/98 ,  H01L23/485 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L27/14634 ,  H01L2224/1413120130101 ,  H01L2224/811320130101 ,  H01L2224/8194820130101 ,  H01L23/544 ,  H01L23/562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0613120130101 ,  H01L2224/8113220130101 ,  H01L2224/8181520130101 ,  H01L2924/35120130101 ,  H01L2924/38120130101 ,  H01L2224/8104820130101 ,  H01L2224/8112220130101 ,  H01L2224/8112920130101 ,  H01L2224/1610520130101 ,  H01L2224/1310920130101 ,  H01L2224/8119420130101 ,  H01L2224/1610820130101 ,  H01L2223/544220130101 ,  H01L2223/5442620130101 ,  H01L2223/5447320130101 ,  H01L2225/0651320130101 ,  H01L2225/0659320130101 ,  H01L27/1469 ,  H01L27/14636

公开(公告)号：EP3417760A1

公开(公告)日：2018-12-26

申请号：EP18185215.3

申请日：2013-10-04

Applicant: OLYMPUS CORPORATION

Inventor： YOSHIDA, Kazuhiro ,  NAKAYAMA, Takashi

IPC: A61B1/00

CPC classification number: H01L27/1464 ,  A61B1/00071 ,  A61B1/0011 ,  A61B1/05 ,  A61B1/051 ,  A61B1/128 ,  H01L27/14636 ,  H01L27/14683 ,  H04N5/2253 ,  H04N2005/2255

Abstract: A semiconductor apparatus capable of being disposed in a narrow space and having high reliability is provided, and a manufacturing method of the semiconductor apparatus. The semiconductor apparatus includes: a semiconductor device chip having a first primary surface and a second primary surface; a wiring board mounted on the second primary surface of the semiconductor device chip and bent such that entirety of the wiring board overlaps the semiconductor device chip when the semiconductor device chip is viewed in a plan view in a thickness direction of the semiconductor device chip; and a resin filled in a space between the second primary surface of the semiconductor device chip and a mounting surface of the wiring board to be mounted on the second primary surface, and positioned such that entirety of the resin overlaps the semiconductor device chip when the semiconductor device chip is viewed in a plan view in the thickness direction of the semiconductor device chip, wherein the resin protrudes from the space along a bending portion on an outer circumferential surface of the wiring board on which the mounting surface is formed in a direction apart from the second primary surface in the thickness direction.

公开(公告)号：EP3410486A1

公开(公告)日：2018-12-05

申请号：EP17178777.3

申请日：2017-06-29

Applicant: ams AG

Inventor： Meynants, Guy

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/146 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14665

Abstract: The semiconductor image sensor device comprises a semiconductor layer (SL) having a main surface (MS) and an opposite rear surface (RS), and a charge carrier generating component (CG) at the main surface. The charge carrier generating component is arranged between a top reflecting layer (R1) and a bottom reflecting layer (R2), which are arranged outside the semiconductor layer.

公开(公告)号：EP3404716A2

公开(公告)日：2018-11-21

申请号：EP18159252.8

申请日：2018-02-28

Applicant: Renesas Electronics Corporation

Inventor： TAKAHASHI, Fumitoshi ,  KUNIKIYO, Tatsuya ,  SATO, Hidenori ,  GOTO, Yotaro

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/1469

Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor (TT) and a photodiode (PD) with a pn junction. In plan view, a reflecting layer (RL) is formed over an n-type region (NR) which configures the photodiode, through an isolation insulating film (SO). The reflecting layer extends over the gate electrode (GE) of the transfer transistor through a cap insulating film (GSO). A first layer signal wiring (ML1) is electrically coupled to both the gate electrode and the reflecting layer through a contact hole (CN) made in an interlayer insulating film (IL) over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.

公开(公告)号：EP3386189A1

公开(公告)日：2018-10-10

申请号：EP16870172.0

申请日：2016-11-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MIYAKE, Yasuo ,  MURAKAMI, Masashi ,  TAMAKI, Tokuhiko ,  SATOU, Yoshiaki

IPC: H04N5/374 ,  H01L27/146

CPC classification number: H04N5/353 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14669 ,  H04N5/3532 ,  H04N5/35554 ,  H04N5/3698 ,  H04N5/378

Abstract: An imaging device includes: unit pixel cells each including a first electrode, a second electrode facing the first electrode, a photoelectric conversion layer between the first electrode and second electrode, a charge accumulation region electrically connected to the first electrode, and a signal detection circuit electrically connected to the charge accumulation region; and a voltage supply circuit electrically connected to the second electrode, the voltage supply circuit supplying a first voltage to the second electrode in an exposure period that is a period for accumulating charges generated by photoelectric conversion in the charge accumulation region, the voltage supply circuit supplying a second voltage that is different from the first voltage to the second electrode in a non-exposure period. The start and end of the exposure period is common to the unit pixel cells.

公开(公告)号：EP2913850B1

公开(公告)日：2018-09-12

申请号：EP13849748.2

申请日：2013-10-04

Applicant: Olympus Corporation

Inventor： YOSHIDA Kazuhiro ,  NAKAYAMA Takashi

IPC: H01L27/14 ,  H04N5/335

CPC classification number: H01L27/1464 ,  A61B1/00071 ,  A61B1/0011 ,  A61B1/05 ,  A61B1/051 ,  A61B1/128 ,  H01L27/14636 ,  H01L27/14683 ,  H04N5/2253 ,  H04N2005/2255

Abstract: An image pickup apparatus 1 includes: an image pickup device chip 10 that has junction terminals 12, which is connected with an image pickup unit 11, on a reverse surface 10SB; a cable 40 having lead wires 41 connected with the image pickup unit 11; and a wiring board 30 that includes junction electrodes 31 formed at a central portion 30M and joined to the junction terminals 12, terminal electrodes 32 formed at extending portions 30S1, 30S2 and connected with the lead wires 41, wirings 33 that connect the junction electrodes 31 and the terminal electrodes 32, and a heat transmission pattern 35 formed in a region where the junction electrodes 31, the terminal electrodes 32 and the wirings 33 are not formed, the extending portions30S1, 30S2 being bent and thereby the wiring board 30 being arranged within a projected plane of the image pickup device chip 10.

公开(公告)号：EP3062346B1

公开(公告)日：2018-08-15

申请号：EP16162111.5

申请日：2012-02-29

Applicant: JVC KENWOOD Corporation

Inventor： KOZLOWSKI, Lester

IPC: H01L27/146 ,  H04N5/378

CPC classification number: H01L27/14634 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/378 ,  H04N5/379

Abstract: An image sensor (10) comprises a PMOS circuit layer (12) comprising an array of pixel elements (122). Each pixel element comprises a pinned photodiode, and an amplifier, the amplifier comprising P-FET transistors. The image sensor also comprises a CMOS layer (18) comprising supporting pixel circuitry, including a global shutter sample and hold circuit, the supporting pixel circuitry comprising N-FET transistors (181). Each pixel element in the PMOS layer is connected to supporting pixel circuitry in the CMOS layer. The sample and hold circuit comprises a trench capacitor formed in the CMOS layer.