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8 条记录 (耗时 0.009 秒)

    Semiconductor memory device
    1.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0209912A2

    公开(公告)日：1987-01-28

    申请号：EP86110330.7

    申请日：1986-07-24

    申请人： HITACHI, LTD. ,  Hitachi VLSI Engineering Corporation

    发明人： Furusawa, Kazunori ,  Nabetani, Shinji ,  Kamigaki, Yoshiaki ,  Terasawa, Masaaki

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14

    摘要： Using a comparatively low supply voltage of, e.g., +5 V and a minus great voltage, the voltage difference between the gate (7) of an MNOS transistor and a P-type well region (2) in which the MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate (1) can be fixed to a comparatively low potential, e.g., about +5 V, so that a P-channel MOSFET formed on the semiconductor substrate (1) operates with an ordinary signal level. Consequently, an EEPROM whose peripheral circuits are constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.

    摘要翻译： 使用例如+ 5V和负大电压的相对较低的电源电压，MNOS晶体管的栅极（7）与其中形成MNOS晶体管的P型阱区（2）之间的电压差是 相对变化以执行MNOS晶体管的写入和擦除。 因此，能够将N型半导体基板（1）的电位固定为比较低的电位，例如+ 5V左右，从而形成在半导体基板（1）上的P沟道MOSFET以通常的信号 水平。 因此，可以提供外围电路由CMOS电路构成的EEPROM。 因此，可以降低EEPROM的功耗。

    Insulated gate field effect transistor
    4.
    发明公开
    Insulated gate field effect transistor 失效
    绝缘栅场效应晶体管

    公开(公告)号：EP0073623A3

    公开(公告)日：1983-11-23

    申请号：EP82304433

    申请日：1982-08-23

    申请人： Hitachi, Ltd.

    发明人： Sunami, Hideo ,  Masuda, Hiroo ,  Shimohigashi, Katsuhiro ,  Kamigaki, Yoshiaki ,  Takeda, Eiji

    IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/7836 ,  H01L29/7838

    摘要： An insulated gate field effect transistor formed in one surface of a semiconductor substrate (1) has a channel, the surface portion of which has an impurity (9) with a conductivity type opposite to that of the substrate (1), and the deeper portion of which has an impurity (8) of the same conductivity type to the substrate. Moreover, the source and/or the drain (6, 7) of the transistor has an impurity layer of a conductivity type opposite to that of the substrate, with an impurity distribution (13, 14) gently sloped. The use of such impurity distributions overcomes the problems of the short-channel effect and reduction of the source-drain breakdown voltage which are present in standard devices. This enables a shorter channel to be used for a given source-drain breakdown voltage which is of advantage in a LSI having a high density of integration.

    摘要翻译： 在半导体衬底（1）的一个表面中形成的绝缘栅极场效应晶体管具有沟道，沟道的表面部分具有与衬底（1）的导电类型相反的导电类型的杂质（9），并且较深部分 其中具有与衬底相同导电类型的杂质（8）。 此外，晶体管的源极和/或漏极（6,7）具有与衬底相反的导电类型的杂质层，杂质分布（13,14）平缓倾斜。 这种杂质分布的使用克服了标准器件中存在的短沟道效应和减少源 - 漏击穿电压的问题。 这使得对于给定的源极 - 漏极击穿电压可以使用较短的沟道，这在具有高集成度的LSI中是有利的。

    Insulated gate field effect transistor
    5.
    发明公开
    Insulated gate field effect transistor 失效
    场效应晶体管用绝缘栅。

    公开(公告)号：EP0073623A2

    公开(公告)日：1983-03-09

    申请号：EP82304433.4

    申请日：1982-08-23

    申请人： Hitachi, Ltd.

    发明人： Sunami, Hideo ,  Masuda, Hiroo ,  Shimohigashi, Katsuhiro ,  Kamigaki, Yoshiaki ,  Takeda, Eiji

    IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/7836 ,  H01L29/7838

    摘要： An insulated gate field effect transistor formed in one surface of a semiconductor substrate (1) has a channel, the surface portion of which has an impurity (9) with a conductivity type opposite to that of the substrate (1), and the deeper portion of which has an impurity (8) of the same conductivity type to the substrate. Moreover, the source and/or the drain (6, 7) of the transistor has an impurity layer of a conductivity type opposite to that of the substrate, with an impurity distribution (13, 14) gently sloped. The use of such impurity distributions overcomes the problems of the short-channel effect and reduction of the source-drain breakdown voltage which are present in standard devices. This enables a shorter channel to be used for a given source-drain breakdown voltage which is of advantage in a LSI having a high density of integration.

    Semiconductor device having a floating gate
    7.
    发明公开
    Semiconductor device having a floating gate 失效
    Halbleiter Anordnung mit schwimmender Gate。

    公开(公告)号：EP0298430A2

    公开(公告)日：1989-01-11

    申请号：EP88110725.4

    申请日：1988-07-05

    申请人： HITACHI, LTD.

    发明人： Kume, Hitoshi ,  Yamamoto, Hideaki ,  Tsukada, Toshihisa ,  Kamigaki, Yoshiaki ,  Adachi, Tetsuo ,  Kure, Tokuo

    IPC分类号： H01L29/00 ,  H01L29/78 ,  H01L27/10

    CPC分类号： H01L29/78612 ,  H01L29/7883

    摘要： In a semiconductor device having a floating gate electrode (16), an electric field to be applied to a gate oxide film (14) is locally modulated in a region where the floating gate electrode (16) overlaps a drain or source region (21). The device of the present invention is well suited for application as a nonvolatile memory cell, and it exhibits a slight leakage current in an erase operation and has a high immunity against the drain disturb phenomenon.

    摘要翻译： 在具有浮置栅极（16）的半导体器件中，施加到栅极氧化膜（14）的电场在浮置栅电极（16）与漏极或源极区域（21）重叠的区域中被局部调制， 。 本发明的器件非常适合作为非易失性存储单元的应用，并且在擦除操作中表现出轻微的漏电流，并且具有对漏泄扰现象的高抗扰性。