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公开(公告)号：EP0501474A2
公开(公告)日：1992-09-02
申请号：EP92103361.9
申请日：1992-02-27
申请人： HITACHI, LTD.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Yamanaka, Hisayoshi , Okishima, Tetsuya , Kawabata, Kiyoshi
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate (10), at least two semiconductor chips (101-106) and a bus line (100). All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer.
Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.
The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线线路的电子电路封装。 要通过总线连接的所有半导体芯片都裸芯片封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 优选地，在多层布线基板的表面上形成有绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且与另一数据总线相连的半导体芯片形成在布线基板的另一侧。
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公开(公告)号：EP0501474B1
公开(公告)日：2003-05-21
申请号：EP92103361.9
申请日：1992-02-27
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Yamanaka, Hisayoshi , Okishima, Tetsuya , Kawabata, Kiyoshi
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
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公开(公告)号：EP0501474A3
公开(公告)日：1993-01-13
申请号：EP92103361.9
申请日：1992-02-27
申请人： HITACHI, LTD.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Yamanaka, Hisayoshi , Okishima, Tetsuya , Kawabata, Kiyoshi
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate (10), at least two semiconductor chips (101-106) and a bus line (100). All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线线路的电子电路封装。 通过总线连接的所有半导体芯片是封装在布线基板上的裸芯片，半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 总线包括两条数据总线，与一条数据总线相连的半导体芯片形成在布线基板的一侧，与另一条数据总线相连的半导体芯片形成在布线基板的另一侧。
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公开(公告)号：EP1394557A2
公开(公告)日：2004-03-03
申请号：EP03025414.8
申请日：1992-02-27
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsuga , Kawabata, Kiyoshi , Yamanaka, Hisayoshi , Okishima, Tetsuya
IPC分类号： G01R31/28
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chips packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. The bus line includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
摘要翻译： 一种电子电路封装，具有布线基板，至少两个半导体芯片和总线。 所有要通过总线连接的半导体芯片都是封装在布线衬底上的裸芯片，并且半导体芯片和布线衬底通过在半导体芯片上形成的引线键合焊盘和布线衬底之间的布线键合连接。 布线基板可以是多层。 总线包括两条数据总线线路，与一根数据总线连接的半导体芯片形成在布线基板的一侧上，与另一数据总线连接的半导体芯片形成在布线基板的另一侧上。
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公开(公告)号：EP0786809A1
公开(公告)日：1997-07-30
申请号：EP97100415.5
申请日：1992-02-27
申请人： HITACHI, LTD.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Kawabata, Kiyoshi , Yamanaka, Hisayoshi , Okishima, Tetsuya
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chips packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. The bus line includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
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公开(公告)号：EP1394557A3
公开(公告)日：2004-10-20
申请号：EP03025414.8
申请日：1992-02-27
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsuga , Kawabata, Kiyoshi , Yamanaka, Hisayoshi , Okishima, Tetsuya
IPC分类号： G01R31/28
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chips packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. The bus line includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线线路的电子电路封装。 通过总线连接的所有半导体芯片是封装在布线基板上的裸芯片，半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层。 总线包括两条数据总线，与一条数据总线相连的半导体芯片形成在布线基板的一侧，与另一条数据总线相连的半导体芯片形成在布线基板的另一侧。
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公开(公告)号：EP0786809B1
公开(公告)日：2004-01-28
申请号：EP97100415.5
申请日：1992-02-27
申请人： Hitachi, Ltd.
发明人： Kanekawa, Nobuyasu , Ihara, Hirokazu , Akiyama, Masatsugu , Kawabata, Kiyoshi , Yamanaka, Hisayoshi , Okishima, Tetsuya
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
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