公开(公告)号：EP4443501A1

公开(公告)日：2024-10-09

申请号：EP22901823.9

申请日：2022-12-01

申请人： LG INNOTEK CO., LTD.

发明人： CHOE, Yu Lim ,  KANG, Tae Gyu ,  LEE, Dong Keon

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L23/50 ,  H01L23/498 ,  H01L23/538

摘要： A semiconductor package according to an embodiment includes a first insulating layer including a cavity; a connection member buried in the cavity of the first insulating layer; and a molding layer buried in the cavity and surrounding the connection member, wherein a width of the molding layer gradually decreases along a direction from a lower surface of the first insulating layer to an upper surface of the first insulating layer.

公开(公告)号：EP4395475A1

公开(公告)日：2024-07-03

申请号：EP22861762.7

申请日：2022-08-26

申请人： LG INNOTEK CO., LTD.

发明人： NAM, Il Sik

IPC分类号： H05K1/11 ,  H05K3/40 ,  H05K3/28 ,  H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

CPC分类号： H05K3/28 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K3/46 ,  H01L23/31 ,  H05K3/40

摘要： A circuit board according to an embodiment includes an insulating layer; a first circuit pattern disposed on the insulating layer; a first protective layer disposed on the insulating layer and including an opening that vertically overlaps an upper surface of the first circuit pattern; a first connection part disposed in the opening; and an electrode part disposed on the first connection part, and wherein a width of an upper surface of the electrode part is smaller than a width of the opening of the first protective layer.

公开(公告)号：EP2191502B1

公开(公告)日：2019-01-16

申请号：EP08802300.7

申请日：2008-09-17

申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

发明人： RAMM, Peter ,  KLUMPP, Armin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/538 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

公开(公告)号：EP3244603A1

公开(公告)日：2017-11-15

申请号：EP15876948.9

申请日：2015-10-29

申请人： Olympus Corporation

发明人： ISHIKAWA, Shinya ,  WATAYA, Yuichi ,  MURAMATSU, Akira

IPC分类号： H04N5/225 ,  A61B1/04 ,  H01L23/12 ,  H01L23/32 ,  H05K9/00

CPC分类号： H01L27/14618 ,  A61B1/00045 ,  A61B1/04 ,  G02B23/2484 ,  H01L23/04 ,  H01L23/041 ,  H01L23/053 ,  H01L23/12 ,  H01L23/32 ,  H01L23/488 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/538 ,  H01L27/146 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L31/0203 ,  H01L2924/0002 ,  H04N5/2256 ,  H04N2005/2255 ,  H01L2924/00

摘要： Provided are an imaging unit, an imaging module, and an endoscope system that make it possible to achieve a reduced diameter of a distal end of an insertion section and to obtain a high-quality image. An imaging unit 10 according to the present invention has a semiconductor package 20 which includes an image sensor and a connection electrode 21 formed on a face f2, a first multi-layer substrate 30 which includes connection electrodes 31, 33 formed on faces f3 and f4 and is connected to the semiconductor package 20 through the connection electrode 31, a second multi-layer substrate 40 which is connected to the first multi-layer substrate 30 with a layer direction of the second multi-layer substrate 40 perpendicular to a layer direction of the first multi-layer substrate 30, an electronic component 51 which is mounted inside the first multi-layer substrate 30, and a cable 60 which is connected to the second multi-layer substrate 40. The second multi-layer substrate 40 is connected to the first multi-layer substrate 30 to form a T shape, and the first multi-layer substrate 30 and the second multi-layer substrate 40 lie within a projected plane in an optical axis direction of the semiconductor package 20.

摘要翻译： 本发明提供一种能够实现插入部的前端的小直径化并且能够得到高品质的图像的摄像部，摄像模块以及内窥镜系统。 根据本发明的成像单元10具有：半导体封装20，其包括图像传感器和形成在面f2上的连接电极21;第一多层基板30，其包括形成在面f3和f4上的连接电极31,33 并且通过连接电极31连接到半导体封装20;第二多层基板40，其与第一多层基板30连接，其中第二多层基板40的层方向垂直于第二多层基板40的层方向 第一多层基板30，安装在第一多层基板30内部的电子部件51以及连接到第二多层基板40的电缆60.第二多层基板40连接到 第一多层基板30形成T形，并且第一多层基板30和第二多层基板40位于半透镜的光轴方向上的投影平面内 nductor包20。

公开(公告)号：EP3242323A1

公开(公告)日：2017-11-08

申请号：EP17168930.0

申请日：2017-05-02

申请人： General Electric Company

发明人： WU, Tao ,  LI, Fei

IPC分类号： H01L23/538 ,  H01L25/07 ,  H05K1/18

CPC分类号： H03K17/66 ,  H01L23/4821 ,  H01L23/538 ,  H01L25/072 ,  H03K17/063 ,  H03K17/567 ,  H03K17/602 ,  H05K1/0203 ,  H05K1/05 ,  H05K1/182 ,  H05K3/0061

摘要： A bridge leg circuit assembly (10, 30) comprising: a circuit board (20, 40), a first active switch die (Q1), and a second active switch die (Q2). The circuit board (20, 40) consists of an insulating plate (14, 34) with a first side and a second side as well as a first conducting layer (11, 31) and a second conducting layer (12, 32) located on the first and second sides of the insulating plate (14, 34), respectively. The second conducting layer (12, 32) consists of a first conducting region (121, 321) and a second conducting region (122, 322) that are insulated from each other. The first active switch die (Q1) consists of an opposing first side and an opposing second side which are embedded into the circuit board (20, 40); the first side of the first active switch die (Q1) is facing and coupled with the first conducting region (121, 321), and the second side of the first active switch die (Q2) is coupled with the second conducting region (122, 322). The second active switch die (Q2) consists of an opposing first side and an opposing second side which are embedded into the circuit board (20, 40); the first side of the second active switch die (Q2) is facing and coupled with the second conducting region (122, 322), and the second side of the second active switch (Q2) is coupled with the first conducting layer (11, 31). Embodiments of the present invention also relate to a full-bridge circuit assembly (50).

摘要翻译： 一种桥臂电路组件（10,30），包括：电路板（20,40），第一有源开关管芯（Q1）和第二有源开关管芯（Q2）。 电路板（20,40）包括具有第一侧和第二侧的绝缘板（14,34）以及位于第一侧和第二侧上的第一导电层（11,31）和第二导电层（12,32） 绝缘板14,34的第一和第二侧。 第二导电层（12,32）由彼此绝缘的第一导电区域（121,321）和第二导电区域（122,322）组成。 第一有源开关管芯（Q1）由嵌入电路板（20,40）中的相对的第一侧和相对的第二侧组成; 第一有源开关管芯Q1的第一侧与第一导电区域121,321相对并且与第一导电区域121,321耦合，并且第一有源开关管芯Q2的第二侧与第二导电区域122相耦合， 322）。 第二有源开关管芯（Q2）由嵌入电路板（20,40）中的相对的第一侧和相对的第二侧组成; 第二有源开关晶片（Q2）的第一侧面对第二导电区域（122,322）并与其耦合，并且第二有源开关（Q2）的第二侧与第一导电层（11,31） ）。 本发明的实施例还涉及全桥电路组件（50）。

公开(公告)号：EP2722904A3

公开(公告)日：2015-11-25

申请号：EP13180791.9

申请日：2013-08-16

申请人： Cree, Inc.

发明人： Ring, Zoltan ,  Hagleitner, Helmut ,  Namishia, Daniel ,  Radulescu, Fabian

IPC分类号： H01L49/02 ,  H01L23/532 ,  C23C28/02 ,  C23C28/00 ,  H01L23/522 ,  C23C18/42 ,  H01L23/538 ,  H01L33/36 ,  H01L33/38 ,  H01L21/20 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/5223 ,  C23C28/023 ,  C23C28/42 ,  H01L21/022 ,  H01L23/3192 ,  H01L23/49534 ,  H01L23/53252 ,  H01L23/538 ,  H01L28/65 ,  H01L28/75 ,  H01L33/36 ,  H01L33/385 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die, which includes a substrate (12), a group of primary conduction sub-layers (26, 30, 34), and a group of separation sub-layers (28, 32), is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.

公开(公告)号：EP2899757A1

公开(公告)日：2015-07-29

申请号：EP13839748.4

申请日：2013-09-13

申请人： Rohm Co., Ltd.

发明人： HANADA, Toshio

IPC分类号： H01L25/07 ,  H01L23/28 ,  H01L25/18 ,  H02M7/48

CPC分类号： H01L23/482 ,  H01L21/50 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/538 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/07 ,  H01L25/072 ,  H01L25/115 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/30107 ,  H02M7/003 ,  H01L2924/00 ,  H01L2224/45099

摘要： The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate. There is provided a power module semiconductor device having a vertical terminal transfermold in which structure thereof is simple and the number of parts is reduced, thereby achieving space saving.

摘要翻译： 的功率半导体模块装置（2）包括：绝缘衬底（10）; 的第一图案（10A）（D）设置在所述绝缘基板（10）; 布置在所述第一图案的半导体芯片（Q）; 电源端子（ST，DT）和信号端子（CS，G，SS）电连接到所述半导体芯片; 和配置的树脂层（12），以覆盖所述半导体芯片和所述绝缘基片。 信号端子被布置成在垂直方向相对于被扩展到所述绝缘基板的一个主表面上。 提供了一种具有一个垂直终端transfermold其中结构的功率模块的半导体装置及其简单，部件数量减少，从而节省空间实现。

公开(公告)号：EP2783393A2

公开(公告)日：2014-10-01

申请号：EP12792149.2

申请日：2012-06-01

申请人： Texas Instruments Incorporated

发明人： WEST, Jeffrey, Alan

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

摘要： A method (100) of protecting through-substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside (101). A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips (102). The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head (104). The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

公开(公告)号：EP2539933A1

公开(公告)日：2013-01-02

申请号：EP11708699.1

申请日：2011-02-22

申请人： Interposers GmbH

发明人： Jakob, Andreas ,  Kaiser, Thomas

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L21/48

CPC分类号： H01L24/14 ,  H01L21/4867 ,  H01L23/538 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11318 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： In a method for producing a semiconductor module (10) comprising at least two semiconductor chips (12, 14) and an interposer (20), which has electrically conductive structures (28) that connect the semiconductor chips (12, 14) to each other, the interposer (20) is imprinted directly on a first (12) one of the semiconductor chips. Upon imprinting the interposer (20), the electrically conductive structures (28) are generated by means of electrically conductive ink (68). The second semiconductor chip (14) is installed on the interposer (20) such that the two semiconductor chips (12, 14) are arranged on top of each other and the interposer (20) forms an intermediate layer between the two semiconductor chips (12, 14).

公开(公告)号：EP2457719A1

公开(公告)日：2012-05-30

申请号：EP10192458.7

申请日：2010-11-24

申请人： Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

发明人： Oosterhuis, Gerrit ,  Maalderink, Herman Hendrikus ,  Rijfers, Andries ,  Houben, René Jos ,  van der Zon, Clemens Maria Bernardus ,  Brouwers, leonardus Antonius Maria

IPC分类号： B29C67/00

CPC分类号： H01R12/71 ,  B29C64/124 ,  B29L2031/3061 ,  B29L2031/3425 ,  B33Y80/00 ,  H01L23/538 ,  H01L2924/0002 ,  H01R43/26 ,  H05K1/0284 ,  H05K3/0014 ,  H05K3/10 ,  H05K2203/072 ,  Y10T29/49208 ,  H01L2924/00

摘要： There is provided a three-dimensional interconnect structure for microelectronic devices and a method for producing such an interconnect structure. The method comprises a step wherein a backbone structure 100 is manufactured using an additive layer-wise manufacturing process 310. The backbone structure 100 comprises a three-dimensional cladding skeleton 104 and a support structure 101. The cladding skeleton comprises layered freeform skeleton parts 105 that will form the electric interconnections between the electric contacts of the interconnect structure after a conductive material 202 is applied on the backbone structure 100. The support structure 101 supports the layered freeform skeleton parts 105. Parts 306 of the support structure 101 may be removed to isolate and/or expose the electric interconnections 205. The cladding skeleton can be embedded by an insulating material 303 for providing a further support.

摘要翻译： 提供了用于微电子器件的三维互连结构以及用于制造这种互连结构的方法。 该方法包括一个步骤，其中使用附加层制造工艺310制造骨架结构100.骨架结构100包括三维包覆骨架104和支撑结构101.包层骨架包括层状自由形骨架部分105， 将导电材料202施加在骨架结构100上之后，将形成互连结构的电触点之间的电互连。支撑结构101支撑分层的自由形骨架部分105.支撑结构101的部分306可以被去除以隔离 和/或暴露电互连205.包层骨架可以被绝缘材料303嵌入以提供另外的支撑。