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公开(公告)号：EP0196054A3
公开(公告)日：1987-04-01
申请号：EP86104059
申请日：1986-03-25
Applicant: HITACHI, LTD.
Inventor： Kajiwara, Ryoichi , Funamoto, Takao , Katoo, Mitsuo , Shida, Tomohiko , Matsuzaka, Takeshi , Wachi, Hiroshi , Takahashi, Kazuya
CPC classification number: H01L23/4336 , H01L23/4332 , H01L24/32 , H01L2224/73253
Abstract: A semiconductor module cooling structure comprises a housing (33) having a passage (45, 46) through which a cooling fluid flows; a cooling block (72,75) to which the cooling fluid is supplied from the housing and which has an electrical insulating layer (36, 59) at the bottom portion and is combined with a semiconductor chip (40) through the electrical insulating layer; and a bellows (34) which is connected between the housing and the cooling block. The cooling fluid is supplied to the cooling block through the bellows. The bellows is formed in a manner such that a plurality of substantially plane ring-like metal plates (4) are laminated, pressed, diffused, joined, and thereafter stretched and molded.
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Patent Agency Ranking
公开(公告)号：EP0196054B1
公开(公告)日：1991-12-11
申请号：EP86104059.0
申请日：1986-03-25
Applicant: HITACHI, LTD.
Inventor： Kajiwara, Ryoichi , Funamoto, Takao , Katoo, Mitsuo , Shida, Tomohiko , Matsuzaka, Takeshi , Wachi, Hiroshi , Takahashi, Kazuya
IPC: H01L23/46
CPC classification number: H01L23/4336 , H01L23/4332 , H01L24/32 , H01L2224/73253
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公开(公告)号：EP0228212A3
公开(公告)日：1989-09-27
申请号：EP86309619.4
申请日：1986-12-10
Applicant: HITACHI, LTD.
Inventor： Funamoto, Takao , Katou, Mituo , Kajiwara, Ryoichi , Matsuzaka, Takeshi , Shida, Tomohiko , Takahashi, Kazuya , Wachi, Hiroshi , Watanabe, Masatoshi , Yamada, Minoru , Sugawara, Katuo , Nakanishi, Keiichirou
CPC classification number: H05K1/0373 , H01L23/473 , H01L23/5383 , H01L23/5385 , H01L2924/0002 , H05K1/0272 , H05K2201/0209 , H05K2201/0251 , H05K2201/064 , H01L2924/00
Abstract: An integrated circuit device has a wiring substrate (2) on one surface of which integrated circuit chips (l) are mounted. A power source substrate (5) of a laminated structure is in contact with the opposite surface of the wiring substrate (2), the power source substrate being of alternate laminations of conductor layers (7) of a heat conductive metal and insulating layers (6) of an electrically insulating material, which layers are bonded together. Means such as pins (4) electrically connect the wiring substrate and the power source substrate to each other, and hence connect the chips (l) to the conductive layers (7), a heat radiating means is provided in at least one of either or both of the conductor layers (7) and the insulating layers (6) and radiates heat, which occurs in the power source substrate (5), to the exterior of the device. Such an integrated circuit device has a power source substrate (5) of a remarkably high heat radiating efficiency, and may permit a high density of integrated circuit chips (l) on the wiring substrate (2).
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公开(公告)号：EP0228212B1
公开(公告)日：1991-08-07
申请号：EP86309619.4
申请日：1986-12-10
Applicant: HITACHI, LTD.
Inventor： Funamoto, Takao , Katou, Mituo , Kajiwara, Ryoichi , Matsuzaka, Takeshi , Shida, Tomohiko , Takahashi, Kazuya , Wachi, Hiroshi , Watanabe, Masatoshi , Yamada, Minoru , Sugawara, Katuo , Nakanishi, Keiichirou
CPC classification number: H05K1/0373 , H01L23/473 , H01L23/5383 , H01L23/5385 , H01L2924/0002 , H05K1/0272 , H05K2201/0209 , H05K2201/0251 , H05K2201/064 , H01L2924/00
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公开(公告)号：EP0228212A2
公开(公告)日：1987-07-08
申请号：EP86309619.4
申请日：1986-12-10
Applicant: HITACHI, LTD.
Inventor： Funamoto, Takao , Katou, Mituo , Kajiwara, Ryoichi , Matsuzaka, Takeshi , Shida, Tomohiko , Takahashi, Kazuya , Wachi, Hiroshi , Watanabe, Masatoshi , Yamada, Minoru , Sugawara, Katuo , Nakanishi, Keiichirou
CPC classification number: H05K1/0373 , H01L23/473 , H01L23/5383 , H01L23/5385 , H01L2924/0002 , H05K1/0272 , H05K2201/0209 , H05K2201/0251 , H05K2201/064 , H01L2924/00
Abstract: An integrated circuit device has a wiring substrate (2) on one surface of which integrated circuit chips (l) are mounted. A power source substrate (5) of a laminated structure is in contact with the opposite surface of the wiring substrate (2), the power source substrate being of alternate laminations of conductor layers (7) of a heat conductive metal and insulating layers (6) of an electrically insulating material, which layers are bonded together. Means such as pins (4) electrically connect the wiring substrate and the power source substrate to each other, and hence connect the chips (l) to the conductive layers (7), a heat radiating means is provided in at least one of either or both of the conductor layers (7) and the insulating layers (6) and radiates heat, which occurs in the power source substrate (5), to the exterior of the device. Such an integrated circuit device has a power source substrate (5) of a remarkably high heat radiating efficiency, and may permit a high density of integrated circuit chips (l) on the wiring substrate (2).
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公开(公告)号：EP0196054A2
公开(公告)日：1986-10-01
申请号：EP86104059.0
申请日：1986-03-25
Applicant: HITACHI, LTD.
Inventor： Kajiwara, Ryoichi , Funamoto, Takao , Katoo, Mitsuo , Shida, Tomohiko , Matsuzaka, Takeshi , Wachi, Hiroshi , Takahashi, Kazuya
IPC: H01L23/46
CPC classification number: H01L23/4336 , H01L23/4332 , H01L24/32 , H01L2224/73253
Abstract: A semiconductor module cooling structure comprises a housing (33) having a passage (45, 46) through which a cooling fluid flows; a cooling block (72,75) to which the cooling fluid is supplied from the housing and which has an electrical insulating layer (36, 59) at the bottom portion and is combined with a semiconductor chip (40) through the electrical insulating layer; and a bellows (34) which is connected between the housing and the cooling block. The cooling fluid is supplied to the cooling block through the bellows. The bellows is formed in a manner such that a plurality of substantially plane ring-like metal plates (4) are laminated, pressed, diffused, joined, and thereafter stretched and molded.
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