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26 条记录 (耗时 0.018 秒)

    Process for fabricating an ASIC device having a gate-array function block
    4.
    发明公开
    Process for fabricating an ASIC device having a gate-array function block 失效
    一种制备具有一个门阵列功能块中的专用集成电路（ASIC）的过程。

    公开(公告)号：EP0609047A2

    公开(公告)日：1994-08-03

    申请号：EP94300533.0

    申请日：1994-01-25

    申请人： HITACHI, LTD.

    发明人： Fukuda, Hideki ,  Hagiwara, Yoshimune ,  Ito, Satoru ,  Torii, Shuichi ,  Kozawa, Tokinori ,  Yamashiro, Osamu

    IPC分类号： H01L21/82 ,  H01L27/02

    CPC分类号： H01L27/0207 ,  H01L21/82

    摘要： An IC device to be newly developed has at least one first function block (11A-11C, 12A, 12B, 14) and at least one second function block (13A, 13B) in which the first and second function blocks of the to-be-newly developed IC device is formed in a single semiconductor substrate, and logic design data of the first function block is available and that of the second function block needs to be newly prepared at a start of fabrication of the IC device. The IC device is, in one embodiment of the present invention, fabricated by starting logic design (53) of the second function block to prepare logic design data of the second function block while doped layers are formed (55) in a semiconductor substrate for the first and second function blocks to provide a semi-completed IC chip, performing (57) mask design of wiring conductor pattern using the logic design data of the first function block and later obtained logic design data of said second function block to prepare mask design data for the IC device, and forming (57) conductor pattern using the mask design data on the semi-completed IC chip to complete a newly developed IC device.

    Development method of data processing system
    5.
    发明公开
    Development method of data processing system 失效
    Entwicklungsverfahrenfürein Datenverarbeitungssystem und intergrierte Halbleiterschaltung。

    公开(公告)号：EP0364743A1

    公开(公告)日：1990-04-25

    申请号：EP89117257.9

    申请日：1989-09-18

    申请人： HITACHI, LTD.

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Sawase, Terumi ,  Hagiwara, Yoshimune

    IPC分类号： G06F15/78 ,  G06F9/24

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： In development of a data processing system applying a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block capable of being written electrically and a logical operation control block utilizing the logical function block as to execute the logic operation, data corresponding to required specification and function of the system is written in the logical function block. Thereby flexibility is obtained for setting and change of the required function for the semiconductor integrated circuit for data processing.
    The semiconductor integrated circuit for data processing also has an operation specification that the logical function block can be written by a writing device for a non-volatile semiconductor storage device capable of being written electrically. Thereby use convenience regarding the function setting of the semiconduc tor integrated circuit for data processing is improved.

    摘要翻译： 在开发应用用于数据处理的半导体集成电路的数据处理系统中，包括能够被电气写入的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算控制块，对应于 系统的所需规格和功能写入逻辑功能块。 从而获得用于设置和改变用于数据处理的半导体集成电路所需功能的灵活性。 用于数据处理的半导体集成电路还具有操作规范，逻辑功能块可以由能够被电写入的非易失性半导体存储装置的写入装置写入。 因此，为了提高用于数据处理的半导体集成电路的功能设置，使用方便。

    Single chip microcomputer
    6.
    发明公开
    Single chip microcomputer 失效
    单片机

    公开(公告)号：EP0361525A2

    公开(公告)日：1990-04-04

    申请号：EP89118106.7

    申请日：1989-09-29

    申请人： HITACHI, LTD.

    发明人： Sawase, Terumi ,  Hagiwara, Yoshimune ,  Nakamura, Hideo ,  Hatori, Hiroyuki ,  Baba, Shirou ,  Akao, Yasushi

    IPC分类号： G06F15/78

    CPC分类号： G06F9/3879 ,  G06F9/24 ,  G06F9/3897 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867

    摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of ad­dress register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrical­ly writable non-volatile semiconductor memory device. Informa­tion can be externally written into the non-volatile semicon­ductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally sup­plied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

    摘要翻译： 单片微机包括控制电路（12a，12b），处理电路（13a，13b）和多个地址寄存器 - 状态寄存器对。 形成在控制电路（12a，12b）内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入逻辑单元中包括的非易失性半导体存储器中，并且多个地址寄存器 - 状态寄存器对可以被任意选择。 结果，逻辑单元的逻辑功能可以根据外部提供的信息任意建立。 通过这样任意形成的逻辑功能可以满足各种用户的需求规格。

    Single-chip microcomputer
    7.
    发明公开
    Single-chip microcomputer 失效
    艾因 - 芯片Mikrocomputer。

    公开(公告)号：EP0306962A2

    公开(公告)日：1989-03-15

    申请号：EP88114710.2

    申请日：1988-09-08

    申请人： HITACHI, LTD.

    发明人： Sawase, Terumi ,  Noguchi, Kouki ,  Nakamura, Hideo ,  Akao, Yasushi ,  Baba, Shiro ,  Hagiwara, Yoshimune

    IPC分类号： G06F9/24 ,  G06F15/78

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A logic circuit (6) built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby a logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

    摘要翻译： 构建在单片微处理器中的逻辑电路（6）由电可编程存储器元件构成，并且信息从外部写入存储器元件，从而可以构建具有任何期望的逻辑功能的逻辑电路。 可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

    An adder for floating point data
    8.
    发明公开
    An adder for floating point data 失效
    用于浮点数据的添加器

    公开(公告)号：EP0182963A3

    公开(公告)日：1986-10-01

    申请号：EP85107059

    申请日：1981-10-27

    申请人： HITACHI, LTD. ,  HITACHI DENSHI KABUSHIKI KAISHA

    发明人： Hagiwara, Yoshimune ,  Sugiyama, Shizuo ,  Maeda, Narimichi ,  Yumoto, Osamu ,  Akazawa, Takashi ,  Kobayashi, Masahito ,  Kita, Yasuhiro ,  Kita, Yuzo

    IPC分类号： G06F07/50 ,  G06F05/00 ,  H03M07/24

    CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F7/49921 ,  G06F2207/3856

    摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.