-
公开(公告)号：EP4270684A1
公开(公告)日：2023-11-01
申请号：EP22774048.7
申请日：2022-03-10
发明人： CHEN, Zongxun , LI, Jiankang , PEI, Huan , ZHU, Jiang
IPC分类号： H01R33/76
摘要： This application provides an electronic assembly and an electronic device. The electronic assembly includes a first electronic component, a second electronic component, and an electrical connector. The first electronic component and the second electronic component are electrically connected by using the electrical connector. The electrical connector includes a terminal and a first multilayer circuit board. The terminal includes a signal terminal and a ground terminal. The signal terminal is electrically connected to a signal interface of the first electronic component and a signal interface of the second electronic component. Signal terminals configured to transmit a same signal are one group of signal terminals, and at least one ground terminal is disposed between any two adjacent groups of signal terminals. The first multilayer circuit board includes at least one layer of first ground copper sheet. The first electronic component includes a second multilayer circuit board, and the second multilayer circuit board includes at least one layer of second ground copper sheet. The ground terminal is electrically connected to the first ground copper sheet and the second ground copper sheet, to form a shielding cage with good sealing performance. The electronic assembly has a strong interference shielding capability, and may support a high signal transmission rate.
-
公开(公告)号：EP3779991A1
公开(公告)日：2021-02-17
申请号：EP19802826.8
申请日：2019-03-01
发明人： LI, Yongyao , YU, Jun , WANG, Guoyu , LI, Jiankang , LI, You , HONG, Ruihui
摘要： A data strobe signal DQS position adjustment method and apparatus are disclosed. The method includes: obtaining margin effective widths of all data signals DQs in a transmission bus; determining a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary; calculating a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training; and adjusting a delay line DL of the DQS to the first central position. According to this method, a margin of a setup time and a margin of a hold time in which a DQS samples a data signal at a first central position are maximized, thereby avoiding an error code during data reading and writing, and improving reliability of data read and write operations.
-
公开(公告)号：EP4116836A1
公开(公告)日：2023-01-11
申请号：EP22175587.9
申请日：2019-01-07
发明人： LI, Yongyao , ZHU, Jiang , LUO, Fei , LI, Jiankang , MA, Yulong
摘要： This application provides an equalization time configuration method, applied to a processor system in which a PCIe or CCIX bus is used. The method includes: first determining a working PHY type of a master chip and a working PHY type of a slave chip (S103); and then determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip (S107), and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip (S107). This solution can help reduce a quantity of link negotiation failures resulting from equalization time insufficiency.
-
公开(公告)号：EP3779711A1
公开(公告)日：2021-02-17
申请号：EP19806439.6
申请日：2019-01-07
发明人： LI, Yongyao , ZHU, Jiang , LUO, Fei , LI, Jiankang , MA, Yulong
摘要： This application provides an equalization time configuration method, applied to a processor system in which a PCIe or CCIX bus is used. The method includes: first determining a working PHY type of a master chip and a working PHY type of a slave chip; and then determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip. This solution can help reduce a quantity of link negotiation failures resulting from equalization time insufficiency. This application further provides an apparatus and a communications system that perform the method, and a chip mentioned when the method is performed.
-
公开(公告)号：EP4387177A1
公开(公告)日：2024-06-19
申请号：EP22866333.2
申请日：2022-08-12
发明人： LUO, Junping , PAN, Wei , NIE, Er , LI, Jiankang
IPC分类号： H04L25/03
CPC分类号： H04L25/03
摘要： A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link between the first device and the second device is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started, so that time during which the communication link is idle can be effectively used, and a large quantity of transmitter equalization parameters can be evaluated, to obtain an appropriate transmitter equalization parameter. This ensures efficiency of transmitter equalization parameter evaluation.
-
公开(公告)号：EP3859541A1
公开(公告)日：2021-08-04
申请号：EP20735893.8
申请日：2020-01-02
发明人： LI, Yongyao , LUO, Fei , LI, Jiankang , WAN, Jie , JIA, Gongxian
摘要： This application provides a retimer application system, to help reduce a transmission delay. The application system includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter, to complete the second link training between the primary chip and the secondary chip.
-
7.发明公开
公开(公告)号：EP4322165A1
公开(公告)日：2024-02-14
申请号：EP22814954.8
申请日：2022-05-05
发明人： XU, Shibin , WANG, Kejian , LUO, Fei , LI, Jiankang
摘要： Embodiments of this application disclose a data interface equalization adjustment method and apparatus, a device, and a storage medium, and relate to the field of data interface technologies. The method includes: A second device determines equalization parameter indication information of a first transmitter TX on a first data interface. The second device sends a first equalization training sequence block ETSB to a corresponding RX on the first data interface through a TX on a second data interface, where the first ETSB carries the equalization parameter indication information and equalization target indication information, and the equalization target indication information indicates that the first TX is an equalization target. The first device determines the equalization target to be the first TX based on the equalization target indication information, and adjusts an equalization parameter of the first TX to an equalization parameter indicated by the equalization parameter indication information. According to this application, equalization adjustment can be performed on a data interface having different quantities of TXs and RXs.
-
公开(公告)号：EP4002696A1
公开(公告)日：2022-05-25
申请号：EP21193006.0
申请日：2018-11-06
发明人： LI, Yongyao , LI, Jiankang , YU, Jun , ZHU, Jiang , LUO, Fei
摘要： This application provides a link adjustment circuit. The link adjustment circuit comprises a link status circuit and a phase locked loop control circuit, wherein the link status circuit is configured to obtain a signal transmitted in a data channel circuit; the link status circuit is further configured to obtain link status information based on the obtained signal; the link status circuit is further configured to determine, based on the link status information, that a rate of a link needs to be changed; the phase locked loop control circuit is configured to: when the link status circuit determines that the rate of the link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate, wherein the target phase locked loop is an unused phase locked loop in at least two phase locked loops; the link status circuit is further configured to detect that the link enters a rate-changing state; and the phase locked loop control circuit is further configured to switch a currently used phase locked loop to the target phase locked loop when the link status circuit detects that the link enters the rate-changing state.
-
公开(公告)号：EP3885923A1
公开(公告)日：2021-09-29
申请号：EP20744674.1
申请日：2020-01-21
发明人： LI, Yongyao , LUO, Fei , LI, Jiankang , ZHU, Jiang , ZENG, Jieping
IPC分类号： G06F13/40
摘要： This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to: move the data in by using the receive clock, and move the data out by using the receive clock. The transmitter circuit is configured to send, by using the receive clock, the sent data moved out from the elastic buffer.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.013 秒)
