公开(公告)号：EP2499667A1

公开(公告)日：2012-09-19

申请号：EP09851339.3

申请日：2009-11-13

申请人： Hewlett-Packard Development Company, L.P.

发明人： MURALIMANOHAR, Naveen ,  JOUPPI, Norman, Paul

IPC分类号： H01L23/043

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C7/1069 ,  G11C7/1078 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

摘要翻译： 一种包括驻留在堆叠式存储器上的存储器裸片的系统和方法，所述存储器裸片被组织成包括数据的多个垫子。 该系统和方法还包括驻留在堆叠存储器上的附加存储器管芯，该附加存储器管芯被组织成附加的多个垫并且通过硅通孔（TSV）连接到存储器管芯，该数据将沿着TSV传输。

公开(公告)号：EP2529312A2

公开(公告)日：2012-12-05

申请号：EP11737662.4

申请日：2011-01-27

申请人： Hewlett Packard Development Company, L.P.

发明人： MURALIMANOHAR, Naveen ,  JOUPPI, Norman, Paul

IPC分类号： G06F13/16 ,  G06F13/38 ,  G06F12/00

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F13/1642

摘要： A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.

公开(公告)号：EP2951834A1

公开(公告)日：2015-12-09

申请号：EP13874163.2

申请日：2013-01-31

申请人： Hewlett-Packard Development Company, L.P.

发明人： MURALIMANOHAR, Naveen ,  YOON, Han Bin ,  JOUPPI, Norman, Paul

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C13/0061 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2272 ,  Y02D10/13

摘要： A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.

公开(公告)号：EP2203768A1

公开(公告)日：2010-07-07

申请号：EP08841755.5

申请日：2008-10-23

申请人： Hewlett-Packard Development Company, L.P.

发明人： BEAUSOLEIL, Raymond G, ,  FIORENTINO, Marco ,  JOUPPI, Norman, Paul ,  BINKERT, Nathan, Lorenzo ,  SCHREIBER, Robert, Samuel ,  XU, Qianfan

IPC分类号： G02B6/12

CPC分类号： G02B6/43 ,  H04B10/801

摘要： Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect (108) comprises a plurality of on-chip waveguides (308). Additionally, the photonic interconnect may include a plurality of off-chip waveguides (310,620), and at least one optoelectronic converter (306). The at least one optoelectronic converter (306) can be photonically coupled to a portion of the plurality of on-chip waveguides (308), can be photonically coupled to a portion of the plurality of off-chip waveguides (310,620), and is in electronic communication with at least one computer system component (615-618).