公开(公告)号：EP4413570A1

公开(公告)日：2024-08-14

申请号：EP22879203.2

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： CUI, Mingdong ,  WANG, Hongmei ,  GIDUTURI, Hari

IPC: G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G06F3/06

CPC classification number: G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0061 ,  G11C5/145 ,  G11C8/08

公开(公告)号：EP3200191B1

公开(公告)日：2018-12-05

申请号：EP16204024.0

申请日：2016-12-14

Applicant: NXP USA, Inc.

Inventor： Choy, Jon Scott

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1659 ,  G11C11/1693 ,  G11C11/1695 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/74 ,  G11C2213/79

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

公开(公告)号：EP3201925B1

公开(公告)日：2018-09-26

申请号：EP15760047.9

申请日：2015-08-30

Applicant: SanDisk Technologies LLC

Inventor： SIAU, Chang ,  LEE, Jeffrey Koon Yee ,  YAN, Tianhong ,  CHEN, Yingchang ,  BALAKRISHNAN, Gopinath ,  LIU, Tz-Yi

IPC: G11C11/16 ,  G11C13/00 ,  G11C16/28 ,  G11C16/32

CPC classification number: G11C13/004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C16/28 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0054

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

公开(公告)号：EP3161832A4

公开(公告)日：2018-04-25

申请号：EP15812283

申请日：2015-05-13

Applicant: INTEL CORP

Inventor： SRINIVASAN BALAJI ,  RIVERS DOYLE ,  KAU DERCHANG ,  GOLDMAN MATTHEW

IPC: G11C13/02 ,  G11C7/10

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

公开(公告)号：EP3282449A1

公开(公告)日：2018-02-14

申请号：EP15893702.9

申请日：2015-06-02

Applicant: Huawei Technologies Co. Ltd.

Inventor： ZHANG, Yide ,  ZENG, Zhigang ,  ZHU, Yidong ,  CAO, Mingfu ,  ZHAO, Junfeng

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C8/16 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79

Abstract: A circuit (100) is provided. A first end (108) of a resistive random access memory (102) included in the circuit (100) is a first end of the circuit (100), and a second end (116) of the resistive random access memory is connected to a first end (118) of a first switching device (104) and a first end (120) of a second switching device (106) separately, where a threshold voltage of the resistive random access memory (102) is U; a second end (112) of the first switching device (104) is a second end of the circuit; a second end of the second switching device (106) is a third end (110) of the circuit; the first switching device (104) further includes a first control end (114); the second switching device (106) further includes a second control end (122); and the first control end (114) and the second control end (122) are configured to make the first switching device (104) closed and make the second switching device (106) open at the same time, or to make the first switching device (104) open and make the second switching device (106) closed at the same time. Therefore, a working status of the resistive random access memory (102) is flexibly controlled.

Abstract translation: 电路（100）被提供。 包括在电路（100）中的电阻随机存取存储器（102）的第一端（108）是电路（100）的第一端，并且电阻式随机存取存储器的第二端（116）连接到 第一开关装置104的第一端118与第二开关装置106的第一端120分开，其中电阻式随机存取存储器102的阈值电压为U; 所述第一开关装置（104）的第二端（112）是所述电路的第二端; 所述第二开关装置（106）的第二端是所述电路的第三端（110） 第一开关装置（104）还包括第一控制端（114）; 所述第二开关装置（106）还包括第二控制端（122）; ，第一控制端（114）和第二控制端（122）用于使第一开关装置（104）闭合并使第二开关装置（106）同时断开，或者使第一开关装置 （104）打开并使第二开关装置（106）同时闭合。 因此，电阻随机存取存储器（102）的工作状态被灵活控制。

公开(公告)号：EP3200191A1

公开(公告)日：2017-08-02

申请号：EP16204024.0

申请日：2016-12-14

Applicant: NXP USA, Inc.

Inventor： Choy, Jon Scott

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1659 ,  G11C11/1693 ,  G11C11/1695 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/74 ,  G11C2213/79

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

Abstract translation: 在非易失性存储器中，执行感测操作以读取非易失性（NV）元件的方法包括第一阶段和第二阶段。 在第一阶段期间，NV元件经由感测路径晶体管耦合到放大器级的第一输入处的第一电容元件，并且参考单元经由参考感测路径晶体管耦合到第二输入处的第二电容元件 放大器阶段。 在第二阶段期间，NV元件经由感测路径晶体管耦合到第二电容元件，并且参考单元经由参考感测路径晶体管耦合到第一电容元件。 在第一阶段期间，第一和第二电容性元件分别被初始化为表示NV元件和参考单元的状态的电压。 在第二阶段，两个电压之间的电压差被放大。

公开(公告)号：EP2678864A4

公开(公告)日：2017-03-22

申请号：EP12749593

申请日：2012-02-23

Applicant: MICRON TECHNOLOGY INC

Inventor： JOHNSON ADAM D

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2211/5631 ,  G11C2211/5642

Abstract: The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.

Abstract translation: 本公开包括电阻式存储器感测方法和装置。 一种这样的方法包括对耦合到电阻存储器单元阵列的所选导线的一组单元执行基于电压的多通道感测操作。 基于电压的多通道感测操作可以包括提供响应于在相应数字的每个期间连续施加到所选导线的多个不同感测电压中的至少一个进行至少阈值量的电流的组的指示 并且对于多个遍的每个连续遍次，禁用与被确定已经执行与多个遍中的先前一个相关联的阈值电流量的那些小区相对应的数据线。

公开(公告)号：EP3008731A4

公开(公告)日：2017-02-22

申请号：EP14811475

申请日：2014-06-09

Applicant: MICRON TECHNOLOGY INC

Inventor： OTSUKA WATARU ,  KUNIHIRO TAKAFUMI ,  TSUSHIMA TOMOHITO ,  KITAGAWA MAKOTO ,  SUMINO JUN

IPC: G11C13/00 ,  H01L27/10

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：EP3125249A1

公开(公告)日：2017-02-01

申请号：EP16181948.7

申请日：2016-07-29

Applicant: Nantero, Inc.

Inventor： BERTIN, Claude L. ,  ROSENDALE, Glen

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/025 ,  G11C23/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2213/35 ,  G11C2213/82 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796 ,  Y10S977/94

Abstract: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

Abstract translation: 公开了一种用于电阻变化元件阵列的高速存储器电路架构。 一组电阻变化元件组织成行和列，每列由字线和每行由两个位线提供服务。 每行电阻变化元件包括一对参考元件和读出放大器。 参考元件是在对应于SET条件的电阻和对应于阵列中使用的电阻变化元件内的RESET条件的电阻之间具有电阻值的电阻元件。 通过将一行的位线之一通过由字线选择的电阻变化元件放电并同时对行的位线中的另一个通过参考元件进行放电，并比较两条线上的放电速率来执行高速读操作 使用行的读出放大器。 存储状态数据作为高速同步数据脉冲发送到输出数据总线。 从外部同步数据总线接收高速数据，并通过存储器阵列配置中的电阻变化元件内的PROGRAM操作存储高速数据。

公开(公告)号：EP3048612A2

公开(公告)日：2016-07-27

申请号：EP16152133.1

申请日：2016-01-20

Applicant: Nantero, Inc.

Inventor： BERTIN, Claude L. ,  CLEVELAND, Lee

IPC: G11C13/00 ,  G11C13/02

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/025 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

Abstract translation: 公开了用于读取和编程1-R电阻变化元件阵列内的一个或多个电阻变化元件的方法。 这些方法包括使用测量和存储元件来测量阵列内的一个或多个选定单元的电响应，然后将所存储的电响应与阵列内的参考元件的电响应进行比较，以确定一个或多个 选定的细胞。 这些方法还包括编程方法，其中可选择的限流元件被用来允许或禁止编程电流分别流过选定和未选择的单元。 这些方法还包括编程方法，其使用阵列线的特定偏置来仅通过选定的单元提供足够的编程电流。