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    Semiconductor integrated circuit device
    2.
    发明公开
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：EP0907183A2

    公开(公告)日：1999-04-07

    申请号：EP98117000.4

    申请日：1998-09-08

    申请人： Hitachi, Ltd. ,  Hitachi ULSI Systems Co.,Ltd.

    发明人： Sasaki, Toshio ,  Tanaka, Yuji ,  Yanagisawa, Kazumasa ,  Tanaka, Hitoshi ,  Sato, Jun ,  Miyamoto, Takashi ,  Ohtsuka, Mariko ,  Nakanishi, Satoru ,  Ayukawa, Kazushige ,  Watanabe, Takao

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12

    摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

    摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器堆和为多个存储器堆提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路以对应于各个存储器堆并且以级联形式电连接。 初始级运算电路的输入端提供有地址设置固定地址信号。 提供给下一个和随后的运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器堆的信号）。 与上面提到的每个算术电路相关地提供的比较器对存储器访问时输入的地址信号和地址信号之间的一致性进行比较。 根据得到的一致信号选择相应的存储器块。

    A semiconductor integrated circuit
    3.
    发明公开
    A semiconductor integrated circuit 失效
    Eine integrierte Halbleiterschaltung。

    公开(公告)号：EP0676764A2

    公开(公告)日：1995-10-11

    申请号：EP95302121.9

    申请日：1995-03-29

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Nakagome, Yoshinobu ,  Ishikura, Kazuo ,  Nakagawa, Tetsuya ,  Kiuchi, Atsushi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F17/10 ,  G06F17/15 ,  G06K9/4642

    摘要： Herein disclosed is a semiconductor integrated circuit capable of executing processing operations using two-dimensional data in a high parallelism and at a high speed.
    The semiconductor integrated circuit comprises: a two-dimensional memory array (MAR); a parallel data transfer circuit (TRC) for transferring the data read out in parallel through data lines, in parallel to a processing circuit group by selecting the word lines of the two-dimensional memory array; and the processing circuit group (PE) for executing processing operations in parallel by using the data transferred from said parallel data transfer circuit. Each of the processing circuits can make access to the plurality of series word lines of said two-dimensional memory array and the data lines through the parallel data transfer circuit, and the data lines of the two-dimensional memory array, to which a plurality of adjoining processing circuits can make access, have an overlapped range.
    Since the data lines of the two-dimensional memory array, to which the adjoining processing circuits can make access, have an overlapped range, the convolution processing operations or the like can be ex ecuted in parallel for the two-dimensional data stored in the two-dimensional memory array.

    摘要翻译： 这里公开的是能够以高并行性和高速执行使用二维数据的处理操作的半导体集成电路。 半导体集成电路包括：二维存储器阵列（MAR）; 并行数据传输电路（TRC），用于通过选择二维存储器阵列的字线，将通过数据线并行读出的数据并行地传送到处理电路组; 以及用于通过使用从所述并行数据传送电路传送的数据并行执行处理操作的处理电路组（PE）。 每个处理电路可以通过并行数据传输电路和二维存储器阵列的数据线访问所述二维存储器阵列的多个串行字线和数据线，多个 相邻的处理电路可以进行访问，具有重叠的范围。 由于相邻的处理电路可以进行访问的二维存储器阵列的数据线具有重叠的范围，所以可以并行地对存储在两个存储器中的二维数据进行卷积处理操作等 维数内存数组。

    Semiconductor device
    4.
    发明公开
    Semiconductor device 失效
    Halbleitereinrichtung。

    公开(公告)号：EP0433271A2

    公开(公告)日：1991-06-19

    申请号：EP91103267.0

    申请日：1986-07-10

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Kitukawa, Goro ,  Hori, Ryoichi ,  Itoh, Kiyoo ,  Kawajiri, Yoshiki ,  Kawahara, Takayuki

    IPC分类号： H03K19/00 ,  H03K17/693 ,  G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/12 ,  H03K5/08 ,  H03K17/693 ,  H03K19/017 ,  H03K19/017518 ,  H03K19/09448 ,  H03K2217/0036

    摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages.
    In an aspect of performance, the semiconductor device is constructed of a circuit which includes field effect transistors (25, 27, 29), and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (C) which controls the above circuit.
    In another aspect of performance, first switching means is interposed between a first reference voltage and can input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on".
    The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

    摘要翻译： 高集成密度和低功耗的半导体器件防止输入信号的幅度对输出信号的幅度的影响，使得先行电路（C）和后续电路（D）被赋予不同的 参考电压。 在性能方面，半导体器件由包括场效应晶体管（25,27,29）的电路构成，并且其参考一个或多个电压（B1）进行工作，所述参考电压中的至少一个具有 电压值与控制上述电路的前一电路（C）的参考工作电压（VA）不同。 在性能的另一方面，第一开关装置插在驱动器电路的第一参考电压和可输入节点之间，第二开关装置插在前一电路的输出端和驱动器电路的输入端之间，使得当 前一电路的输出信号处于高电平，第二开关在第一开关“截止”时变为“接通”，从而产生更高的电位，并且当前一电路的输出信号为 低电平时，第一开关转为“开”时，第二开关被关闭。 半导体器件适用于使用电压限制器的高密度DRAM和SRAM的那些电路。

    Semiconductor device
    6.
    发明公开
    Semiconductor device 失效
    半导体器件

    公开(公告)号：EP0433271A3

    公开(公告)日：1991-11-06

    申请号：EP91103267.0

    申请日：1986-07-10

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Kitukawa, Goro ,  Hori, Ryoichi ,  Itoh, Kiyoo ,  Kawajiri, Yoshiki ,  Kawahara, Takayuki

    IPC分类号： H03K19/00 ,  H03K17/693 ,  G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/12 ,  H03K5/08 ,  H03K17/693 ,  H03K19/017 ,  H03K19/017518 ,  H03K19/09448 ,  H03K2217/0036

    摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages. In an aspect of performance, the semiconductor device is constructed of a circuit which includes field effect transistors (25, 27, 29), and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (C) which controls the above circuit. In another aspect of performance, first switching means is interposed between a first reference voltage and can input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on". The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

    摘要翻译： 高积分密度和低功耗的半导体器件以前向电路（C）和后向电路（D）被赋予不同的方式来防止输入信号的幅度对输出信号的幅度的影响 参考电压。 在性能方面，半导体器件由包括场效应晶体管（25,27,29）并且参照一个或多个电压（B1）操作的电路构成，至少一个参考电压具有 电压值不同于控制上述电路的在前电路（C）的参考工作电压（VA）。 在性能的另一方面，第一开关装置插入在驱动电路的第一参考电压和罐输入节点之间，并且第二开关装置插在前一电路的输出和驱动电路的输入之间，从而当 前一电路的输出信号处于高电平时，第二开关在第一开关被关断时导通，从而产生更高的电位，并且当前一电路的输出信号处于 低电平时，第一开关打开时，第二开关关闭。 该半导体器件适用于使用电压限制器的高密度DRAM和SRAM的那些电路。

    Neural network processing system using semiconductor memories
    7.
    发明公开
    Neural network processing system using semiconductor memories 失效
    Halbleiterspeicher benutzendes神经元Netzwerk。

    公开(公告)号：EP0438800A2

    公开(公告)日：1991-07-31

    申请号：EP90125680.0

    申请日：1990-12-28

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Kimura, Katsutaka ,  Itoh, Kiyoo ,  Kawajiri, Yoshiki

    IPC分类号： G06F13/00 ,  G06F15/80

    CPC分类号： G06N3/063

    摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

    摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 处理电路，用于执行用于确定存储在所述存储电路中的数据的乘积，和和非线性转换的神经元输出的处理，输出值与其期望值的比较以及学习所需的处理; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以完成确定诸如乘积或和的中子输出值所需的至少一部分处理 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

    Semiconductor device having bipolar transistor and insulated gate field effect transistor
    9.
    发明公开
    Semiconductor device having bipolar transistor and insulated gate field effect transistor 失效
    具有双极晶体管和绝缘栅型场效应晶体管的半导体装置。

    公开(公告)号：EP0209805A2

    公开(公告)日：1987-01-28

    申请号：EP86109470.4

    申请日：1986-07-10

    申请人： HITACHI, LTD.

    发明人： Watanabe, Takao ,  Kitukawa, Goro ,  Hori, Ryoichi ,  Itoh, Kiyoo ,  Kawajiri, Yoshiki ,  Kawahara, Takayuki

    IPC分类号： H03K5/02 ,  H03K19/08 ,  H03K19/01 ,  H03K19/096 ,  G11C7/00

    CPC分类号： G11C8/10 ,  G11C7/12 ,  H03K5/08 ,  H03K17/693 ,  H03K19/017 ,  H03K19/017518 ,  H03K19/09448 ,  H03K2217/0036

    摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages.
    In an aspect of performance, the semiconductor device is constructed of a circuit which includes a bipolar transistor (26) and an insulated-gate field effect transistor (25, 27, 291, and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (CI which controls the above circuit.
    In another aspect of performance, first switching means is interposed between a first reference voltage and an input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on".
    The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

    State monitoring apparatus and state monitoring method of railway car, and railway car
    10.
    发明授权
    State monitoring apparatus and state monitoring method of railway car, and railway car 有权
    铁路车辆和铁路车辆的状态监测装置和状态监测方法

    公开(公告)号：EP2436574B1

    公开(公告)日：2018-05-09

    申请号：EP11250239.8

    申请日：2011-03-02

    申请人： Hitachi, Ltd.

    发明人： Furutani, Ryo ,  Goda, Kenjiro ,  Iwasaki, Katsuyuki ,  Watanabe, Takao

    IPC分类号： B61F9/00 ,  B61L15/00

    CPC分类号： B61F9/005 ,  B61L15/0081

    摘要： The invention provides a state monitoring apparatus and a state monitoring method of a railway car, and a railway car capable of detecting or sensing a defect prior to the occurrence of a serious defect without having to set up thresholds corresponding to various traveling speed patterns. The railway car comprises a vibration detector for detecting a vibration of the railway car, and a defect detection system for detecting defect of the railway car using a signal output from the vibration detector, wherein the vibration detector includes a vibration detection means for detecting the vibration of the railway car from a vibration acceleration of the car body, and the defect detection system includes a filtering means for detecting two or more different frequency band components based on the car body vibration acceleration from the vibration detection means, an amplitude ratio computing means for computing an amplitude ratio of two or more car body vibration accelerations detected via the filtering means, and a defect determination processing means for determining defect based on the result of the amplitude ratio computing means.