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公开(公告)号：EP0646873B1
公开(公告)日：2008-10-08
申请号：EP94112520.5
申请日：1994-08-10
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译： 一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线具有与其连接的外围模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。 单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。 此外，隔离所需要的没有运行速度的外围模块，从而可以降低功耗。
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公开(公告)号：EP0741358A3
公开(公告)日：1997-04-16
申请号：EP96302800.6
申请日：1996-04-22
申请人： HITACHI, LTD.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
IPC分类号： G06F15/78
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
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公开(公告)号：EP0741358B1
公开(公告)日：2001-08-16
申请号：EP96302800.6
申请日：1996-04-22
申请人： Hitachi, Ltd.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
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公开(公告)号：EP0718779A1
公开(公告)日：1996-06-26
申请号：EP96102998.0
申请日：1994-08-10
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译： 一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线具有与其连接的外围模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。 单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。 此外，隔离所需要的没有运行速度的外围模块，从而可以降低功耗。
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公开(公告)号：EP0741358A2
公开(公告)日：1996-11-06
申请号：EP96302800.6
申请日：1996-04-22
申请人： HITACHI, LTD.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
IPC分类号： G06F15/78
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
摘要翻译： 内置存储器分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 由此，CPU核心2可以同时从内置存储器传送两个数据值到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。
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公开(公告)号：EP1028382B1
公开(公告)日：2002-12-04
申请号：EP00109692.4
申请日：1996-04-22
申请人： Hitachi, Ltd.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
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公开(公告)号：EP0646873A2
公开(公告)日：1995-04-05
申请号：EP94112520.5
申请日：1994-08-10
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
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公开(公告)号：EP1028382A1
公开(公告)日：2000-08-16
申请号：EP00109692.4
申请日：1996-04-22
申请人： Hitachi, Ltd.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
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公开(公告)号：EP0718768A1
公开(公告)日：1996-06-26
申请号：EP96102994.9
申请日：1994-08-10
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
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公开(公告)号：EP0646873A3
公开(公告)日：1995-09-20
申请号：EP94112520.5
申请日：1994-08-10
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译： 一种单片微型计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 中断控制器，用于选择性地连接第一总线和第二总线; 第三总线，其具有与其连接的外围模块并且具有比第一总线和第二总线的总线周期更低的总线周期; 以及用于实现第二总线和第三总线之间的数据传输和同步的总线状态控制器。 单片机具有三条分开的内部总线，以降低信号传输路径上的负载容量，从而可以高速完成信号传输。 而且，不需要操作速度的外围模块被隔离，从而可以降低功耗。
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