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公开(公告)号：EP4152376A1
公开(公告)日：2023-03-22
申请号：EP21817520.6
申请日：2021-05-20
发明人： HOU, Zhaozheng , PENG, Hao
IPC分类号： H01L23/367 , H01L23/31 , H01L25/07
摘要： This application provides a chip package structure and an electronic device. The chip package structure in this application includes an insulation layer, a packaging layer, and a heat sink. The heat sink is integrated with the packaging layer. Compared with a common manner of fixing the heat sink to the packaging layer through soldering, gluing, or using a fastener, a defect such as a hole does not easily occur at a position at which the heat sink and the packaging layer are combined, so that heat of the packaging layer can be efficiently transmitted to the heat sink, and a manufacturing process can be reduced. In addition, an electrode of a chip in the chip package structure of this application is led out by using an electrode cable, and an opening is disposed on the insulation layer that covers the electrode cable, to implement an electrical connection between the chip package structure and another structure of the electronic device by using the electrode cable that exposes the opening. In this way, an extension position of the electrode cable and a position of the opening on the insulation layer can be adjusted based on a type of a circuit board on which the chip package structure is installed, so that the chip package structure can be flexibly applied to various types of circuit boards.
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公开(公告)号：EP4120329A3
公开(公告)日：2023-07-05
申请号：EP22184597.7
申请日：2022-07-13
发明人： PENG, Hao , LIAO, Xiaojing
IPC分类号： H01L21/60 , H01L23/538 , H01L23/373 , H01L23/31 , H01L23/433 , H01L23/16
摘要： This application discloses a package structure and a package system. The package structure may be used for packaging various types of chips, and is coupled to a PCB, so as to form the package system. The package structure includes a package base layer (1), a chip (2), a package body (4), and a connecting assembly (5). The package base layer has a first surface and a second surface that are opposite to each other. The chip is coupled to the first surface, and there is a chip pad (21) on a surface that is of the chip and that is away from the package base layer. The package body covers the package base layer and the chip to protect the structure, and the chip pad is wired to a surface of the package body through the connecting assembly. The chip in the package structure is coupled to the package base layer in a mounting manner, and a signal of the chip may be led out to the surface of the package body through the connecting assembly without using pins. This facilitates reduction of a size of the package structure and facilitates implementation of a small size of the package structure. In addition, a structure of the connecting assembly facilitates shortening of a wiring path of a wire bond, so that a possible parasitic effect of the wire bond can be reduced.
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公开(公告)号：EP4125115A1
公开(公告)日：2023-02-01
申请号：EP22186640.3
申请日：2022-07-25
发明人： PENG, Hao , LIAO, Xiaojing , HOU, Zhaozheng
IPC分类号： H01L21/48 , H01L23/13 , H01L23/14 , H01L23/538 , H01L23/552 , H01L23/367 , H01L25/065 , H01L25/00
摘要： This application discloses a chip package assembly, an electronic device, and a preparation method of a chip package assembly. The chip package assembly includes a package substrate, a chip, and a heat dissipation part. The package substrate includes an upper conductive layer, a lower conductive layer, and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode that are disposed opposite to each other, the chip is embedded in the package substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. The upper conductive layer, the lower conductive layer, and the conductive part each have a heat-conducting property. In this application, the chip is connected to the upper conductive layer and the lower conductive layer of the package substrate, so that heat generated by the chip can be bidirectionally conducted for heat dissipation. Further, the heat dissipation part is disposed on the upper conductive layer, so that the chip package assembly can achieve a better heat dissipation effect.
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公开(公告)号：EP4120329A2
公开(公告)日：2023-01-18
申请号：EP22184597.7
申请日：2022-07-13
发明人： PENG, Hao , LIAO, Xiaojing
IPC分类号： H01L21/60 , H01L23/538 , H01L23/373
摘要： This application discloses a package structure and a package system. The package structure may be used for packaging various types of chips, and is coupled to a PCB, so as to form the package system. The package structure includes a package base layer (1), a chip (2), a package body (4), and a connecting assembly (5). The package base layer has a first surface and a second surface that are opposite to each other. The chip is coupled to the first surface, and there is a chip pad (21) on a surface that is of the chip and that is away from the package base layer. The package body covers the package base layer and the chip to protect the structure, and the chip pad is wired to a surface of the package body through the connecting assembly. The chip in the package structure is coupled to the package base layer in a mounting manner, and a signal of the chip may be led out to the surface of the package body through the connecting assembly without using pins. This facilitates reduction of a size of the package structure and facilitates implementation of a small size of the package structure. In addition, a structure of the connecting assembly facilitates shortening of a wiring path of a wire bond, so that a possible parasitic effect of the wire bond can be reduced.
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