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公开(公告)号：EP1618609A4
公开(公告)日：2009-10-28
申请号：EP03816906
申请日：2003-04-30
申请人： IBM
IPC分类号： H01L29/00 , H01L21/44 , H01L23/525
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
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2.发明公开
公开(公告)号：EP1678764A4
公开(公告)日：2011-03-02
申请号：EP04817244
申请日：2004-10-04
申请人： IBM
发明人： ABADEER WAGDI W , FIFIELD JOHN A , TONTI WILLIAM R
IPC分类号： H01L27/12 , H01L21/82 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
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公开(公告)号：EP1581968A4
公开(公告)日：2007-04-18
申请号：EP02808339
申请日：2002-12-20
申请人： IBM
发明人： RANKIN JED H , ABADEER WAGDI W , BROWN JEFFREY S , CHATTY KIRAN V , TONTI WILLIAM R , GAUTHIER ROBERT J JR , FRIED DAVID M
IPC分类号： H01L23/525 , H01L21/82 , H01L21/84 , H01L27/06 , H01L27/118 , H01L27/12
CPC分类号： H01L21/84 , H01L23/5252 , H01L27/0629 , H01L27/11807 , H01L27/1203 , H01L29/785 , H01L29/7854 , H01L2924/0002 , H01L2924/00
摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).
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