公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：EP1573804A4

公开(公告)日：2006-03-08

申请号：EP02798557

申请日：2002-12-19

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66795

Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.